schematic fixed on data input

This commit is contained in:
interfisch 2023-01-22 22:42:16 +01:00
parent 811bde32a0
commit 8a7a669260
6 changed files with 12291 additions and 23 deletions

View File

@ -132,7 +132,7 @@ F1 "Connector_Generic_Conn_01x01" 0 -100 50 H V C CNN
F2 "" 0 0 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
$FPLIST $FPLIST
Connector*:* Connector*:*_1x??_*
$ENDFPLIST $ENDFPLIST
DRAW DRAW
S -50 5 0 -5 1 1 6 N S -50 5 0 -5 1 1 6 N
@ -332,11 +332,8 @@ $FPLIST
CP_* CP_*
$ENDFPLIST $ENDFPLIST
DRAW DRAW
S -90 20 -90 40 0 1 0 N S -90 20 90 40 0 1 0 N
S -90 20 90 20 0 1 0 N
S 90 -20 -90 -40 0 1 0 F S 90 -20 -90 -40 0 1 0 F
S 90 40 -90 40 0 1 0 N
S 90 40 90 20 0 1 0 N
P 2 0 1 0 -70 90 -30 90 N P 2 0 1 0 -70 90 -30 90 N
P 2 0 1 0 -50 110 -50 70 N P 2 0 1 0 -50 110 -50 70 N
X ~ 1 0 150 110 D 50 50 1 1 P X ~ 1 0 150 110 D 50 50 1 1 P
@ -382,7 +379,7 @@ ENDDEF
# #
# Device_R_Network09 # Device_R_Network09
# #
DEF Device_R_Network09 RN 0 0 N N 1 F N DEF Device_R_Network09 RN 0 0 Y N 1 F N
F0 "RN" -500 0 50 V V C CNN F0 "RN" -500 0 50 V V C CNN
F1 "Device_R_Network09" 500 0 50 V V C CNN F1 "Device_R_Network09" 500 0 50 V V C CNN
F2 "Resistor_THT:R_Array_SIP10" 575 0 50 V I C CNN F2 "Resistor_THT:R_Array_SIP10" 575 0 50 V I C CNN
@ -409,7 +406,15 @@ S 70 60 130 -100 0 1 10 N
S 170 60 230 -100 0 1 10 N S 170 60 230 -100 0 1 10 N
S 270 60 330 -100 0 1 10 N S 270 60 330 -100 0 1 10 N
S 370 60 430 -100 0 1 10 N S 370 60 430 -100 0 1 10 N
P 2 0 1 0 -400 100 -400 60 N P 2 0 1 0 -400 -100 -400 -150 N
P 2 0 1 0 -300 -100 -300 -150 N
P 2 0 1 0 -200 -100 -200 -150 N
P 2 0 1 0 -100 -100 -100 -150 N
P 2 0 1 0 0 -100 0 -150 N
P 2 0 1 0 100 -100 100 -150 N
P 2 0 1 0 200 -100 200 -150 N
P 2 0 1 0 300 -100 300 -150 N
P 2 0 1 0 400 -100 400 -150 N
P 4 0 1 0 -400 60 -400 90 -300 90 -300 60 N P 4 0 1 0 -400 60 -400 90 -300 90 -300 60 N
P 4 0 1 0 -300 60 -300 90 -200 90 -200 60 N P 4 0 1 0 -300 60 -300 90 -200 90 -200 60 N
P 4 0 1 0 -200 60 -200 90 -100 90 -100 60 N P 4 0 1 0 -200 60 -200 90 -100 90 -100 60 N
@ -419,15 +424,15 @@ P 4 0 1 0 100 60 100 90 200 90 200 60 N
P 4 0 1 0 200 60 200 90 300 90 300 60 N P 4 0 1 0 200 60 200 90 300 90 300 60 N
P 4 0 1 0 300 60 300 90 400 90 400 60 N P 4 0 1 0 300 60 300 90 400 90 400 60 N
X common 1 -400 200 100 D 50 50 1 1 P X common 1 -400 200 100 D 50 50 1 1 P
X R9 10 400 -200 100 U 50 50 1 1 P X R9 10 400 -200 50 U 50 50 1 1 P
X R1 2 -400 -200 100 U 50 50 1 1 P X R1 2 -400 -200 50 U 50 50 1 1 P
X R2 3 -300 -200 100 U 50 50 1 1 P X R2 3 -300 -200 50 U 50 50 1 1 P
X R3 4 -200 -200 100 U 50 50 1 1 P X R3 4 -200 -200 50 U 50 50 1 1 P
X R4 5 -100 -200 100 U 50 50 1 1 P X R4 5 -100 -200 50 U 50 50 1 1 P
X R5 6 0 -200 100 U 50 50 1 1 P X R5 6 0 -200 50 U 50 50 1 1 P
X R6 7 100 -200 100 U 50 50 1 1 P X R6 7 100 -200 50 U 50 50 1 1 P
X R7 8 200 -200 100 U 50 50 1 1 P X R7 8 200 -200 50 U 50 50 1 1 P
X R8 9 300 -200 100 U 50 50 1 1 P X R8 9 300 -200 50 U 50 50 1 1 P
ENDDRAW ENDDRAW
ENDDEF ENDDEF
# #
@ -478,9 +483,9 @@ $FPLIST
D*DO?35* D*DO?35*
$ENDFPLIST $ENDFPLIST
DRAW DRAW
P 2 0 1 8 -50 50 -50 -50 N P 2 0 1 10 -50 50 -50 -50 N
P 2 0 1 0 50 0 -50 0 N P 2 0 1 0 50 0 -50 0 N
P 4 0 1 8 50 50 50 -50 -50 0 50 50 N P 4 0 1 10 50 50 50 -50 -50 0 50 50 N
X K 1 -150 0 100 R 50 50 1 1 P X K 1 -150 0 100 R 50 50 1 1 P
X A 2 150 0 100 L 50 50 1 1 P X A 2 150 0 100 L 50 50 1 1 P
ENDDRAW ENDDRAW
@ -493,7 +498,7 @@ F0 "U" -150 125 50 H V C CNN
F1 "Regulator_Linear_LM7812_TO220" 0 125 50 H V L CNN F1 "Regulator_Linear_LM7812_TO220" 0 125 50 H V L CNN
F2 "Package_TO_SOT_THT:TO-220-3_Vertical" 0 225 50 H I C CIN F2 "Package_TO_SOT_THT:TO-220-3_Vertical" 0 225 50 H I C CIN
F3 "" 0 -50 50 H I C CNN F3 "" 0 -50 50 H I C CNN
ALIAS LM7806_TO220 LM7808_TO220 LM7809_TO220 LM7810_TO220 LM7812_TO220 LM7815_TO220 LM7818_TO220 LM7824_TO220 LM78M05_TO220 SPX2920U-3.3_TO220 SPX2920U-5.0_TO220 LF15_TO220 LF18_TO220 LF25_TO220 LF33_TO220 LF50_TO220 LF60_TO220 LF80_TO220 LF85_TO220 LF120_TO220 LF47_TO220 LF90_TO220 LM341T-05_TO220 LM341T-12_TO220 LM341T-15_TO220 LM2937xT ALIAS LM7806_TO220 LM7808_TO220 LM7809_TO220 LM7810_TO220 LM7812_TO220 LM7815_TO220 LM7818_TO220 LM7824_TO220 LM78M05_TO220 SPX2920U-3.3_TO220 SPX2920U-5.0_TO220 LF15_TO220 LF18_TO220 LF25_TO220 LF33_TO220 LF50_TO220 LF60_TO220 LF80_TO220 LF85_TO220 LF120_TO220 LF47_TO220 LF90_TO220 LM341T-05_TO220 LM341T-12_TO220 LM341T-15_TO220 LM2937xT LM2931-3.3_TO220 LM2931-5.0_TO220
$FPLIST $FPLIST
TO?220* TO?220*
$ENDFPLIST $ENDFPLIST
@ -560,8 +565,9 @@ F1 "power_VDD" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
DRAW DRAW
C 0 75 25 0 1 0 N P 2 0 1 0 -30 50 0 100 N
P 2 0 1 0 0 0 0 50 N P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 100 30 50 N
X VDD 1 0 0 0 U 50 50 1 1 W N X VDD 1 0 0 0 U 50 50 1 1 W N
ENDDRAW ENDDRAW
ENDDEF ENDDEF
@ -574,8 +580,8 @@ F1 "power_VSS" 0 150 50 H V C CNN
F2 "" 0 0 50 H I C CNN F2 "" 0 0 50 H I C CNN
F3 "" 0 0 50 H I C CNN F3 "" 0 0 50 H I C CNN
DRAW DRAW
C 0 75 25 0 1 0 N P 2 0 1 0 0 0 0 100 N
P 2 0 1 0 0 0 0 50 N P 4 0 1 0 30 50 -30 50 0 100 30 50 F
X VSS 1 0 0 0 U 50 50 1 1 W N X VSS 1 0 0 0 U 50 50 1 1 W N
ENDDRAW ENDDRAW
ENDDEF ENDDEF

View File

@ -0,0 +1,75 @@
{
"board": {
"active_layer": 0,
"active_layer_preset": "",
"auto_track_width": true,
"hidden_nets": [],
"high_contrast_mode": 0,
"net_color_mode": 1,
"opacity": {
"pads": 1.0,
"tracks": 1.0,
"vias": 1.0,
"zones": 0.6
},
"ratsnest_display_mode": 0,
"selection_filter": {
"dimensions": true,
"footprints": true,
"graphics": true,
"keepouts": true,
"lockedItems": true,
"otherItems": true,
"pads": true,
"text": true,
"tracks": true,
"vias": true,
"zones": true
},
"visible_items": [
0,
1,
2,
3,
4,
5,
8,
9,
10,
11,
12,
13,
14,
15,
16,
17,
18,
19,
20,
21,
22,
23,
24,
25,
26,
27,
28,
29,
30,
32,
33,
34,
35,
36
],
"visible_layers": "fffffff_ffffffff",
"zone_display_mode": 0
},
"meta": {
"filename": "annax37623.kicad_prl",
"version": 3
},
"project": {
"files": []
}
}

View File

@ -0,0 +1,325 @@
{
"board": {
"design_settings": {
"defaults": {
"board_outline_line_width": 0.1,
"copper_line_width": 0.2,
"copper_text_size_h": 1.5,
"copper_text_size_v": 1.5,
"copper_text_thickness": 0.3,
"other_line_width": 0.15,
"silk_line_width": 0.15,
"silk_text_size_h": 1.0,
"silk_text_size_v": 1.0,
"silk_text_thickness": 0.15
},
"diff_pair_dimensions": [],
"drc_exclusions": [],
"rules": {
"solder_mask_clearance": 0.0,
"solder_mask_min_width": 0.0
},
"track_widths": [],
"via_dimensions": []
},
"layer_presets": []
},
"boards": [],
"cvpcb": {
"equivalence_files": []
},
"erc": {
"erc_exclusions": [],
"meta": {
"version": 0
},
"pin_map": [
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
1,
0,
1,
2
],
[
0,
1,
0,
0,
0,
0,
1,
1,
2,
1,
1,
2
],
[
0,
0,
0,
0,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
0,
2
],
[
1,
1,
1,
1,
1,
0,
1,
1,
1,
1,
1,
2
],
[
0,
0,
0,
1,
0,
0,
1,
0,
0,
0,
0,
2
],
[
0,
2,
1,
2,
0,
0,
1,
0,
2,
2,
2,
2
],
[
0,
2,
0,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
0,
2,
1,
1,
0,
0,
1,
0,
2,
0,
0,
2
],
[
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2,
2
]
],
"rule_severities": {
"bus_definition_conflict": "error",
"bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error",
"different_unit_footprint": "error",
"different_unit_net": "error",
"duplicate_reference": "error",
"duplicate_sheet_names": "error",
"extra_units": "error",
"global_label_dangling": "warning",
"hier_label_mismatch": "error",
"label_dangling": "error",
"lib_symbol_issues": "warning",
"multiple_net_names": "warning",
"net_not_bus_member": "warning",
"no_connect_connected": "warning",
"no_connect_dangling": "warning",
"pin_not_connected": "error",
"pin_not_driven": "error",
"pin_to_pin": "warning",
"power_pin_not_driven": "error",
"similar_labels": "warning",
"unannotated": "error",
"unit_value_mismatch": "error",
"unresolved_variable": "error",
"wire_dangling": "error"
}
},
"libraries": {
"pinned_footprint_libs": [],
"pinned_symbol_libs": []
},
"meta": {
"filename": "annax37623.kicad_pro",
"version": 1
},
"net_settings": {
"classes": [
{
"bus_width": 12.0,
"clearance": 0.2,
"diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25,
"diff_pair_width": 0.2,
"line_style": 0,
"microvia_diameter": 0.3,
"microvia_drill": 0.1,
"name": "Default",
"pcb_color": "rgba(0, 0, 0, 0.000)",
"schematic_color": "rgba(0, 0, 0, 0.000)",
"track_width": 0.25,
"via_diameter": 0.8,
"via_drill": 0.4,
"wire_width": 6.0
}
],
"meta": {
"version": 2
},
"net_colors": null
},
"pcbnew": {
"last_paths": {
"gencad": "",
"idf": "",
"netlist": "",
"specctra_dsn": "",
"step": "",
"vrml": ""
},
"page_layout_descr_file": ""
},
"schematic": {
"annotate_start_num": 0,
"drawing": {
"default_line_thickness": 6.0,
"default_text_size": 50.0,
"field_names": [],
"intersheets_ref_own_page": false,
"intersheets_ref_prefix": "",
"intersheets_ref_short": false,
"intersheets_ref_show": false,
"intersheets_ref_suffix": "",
"junction_size_choice": 3,
"label_size_ratio": 0.25,
"pin_symbol_size": 25.0,
"text_offset_ratio": 0.08
},
"legacy_lib_dir": "",
"legacy_lib_list": [],
"meta": {
"version": 1
},
"net_format_name": "",
"ngspice": {
"fix_include_paths": true,
"fix_passive_vals": false,
"meta": {
"version": 0
},
"model_mode": 0,
"workbook_filename": ""
},
"page_layout_descr_file": "",
"plot_directory": "",
"spice_adjust_passive_values": false,
"spice_external_command": "spice \"%I\"",
"subpart_first_id": 65,
"subpart_id_separator": 0
},
"sheets": [
[
"d0a0deb1-4f0f-4ede-b730-2c6d67cb9618",
""
]
],
"text_variables": {}
}

File diff suppressed because it is too large Load Diff

Binary file not shown.

After

Width:  |  Height:  |  Size: 28 KiB

Binary file not shown.

After

Width:  |  Height:  |  Size: 28 KiB