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portexpander
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portexpander/platinedehaute.kicad_pcb

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add front panel mount screws
2018-10-07 15:00:25 +00:00
(kicad_pcb (version 20171130) (host pcbnew 5.0.0-fee4fd1~66~ubuntu16.04.1)
start pcb layout
2018-08-26 19:54:32 +00:00
(general
(thickness 1.6)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(drawings 5)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(tracks 627)
start pcb layout
2018-08-26 19:54:32 +00:00
(zones 0)
(modules 92)
(nets 113)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(32 B.Adhes user hide)
(33 F.Adhes user hide)
(34 B.Paste user hide)
(35 F.Paste user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(36 B.SilkS user)
(37 F.SilkS user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(38 B.Mask user hide)
(39 F.Mask user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(40 Dwgs.User user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(41 Cmts.User user hide)
(42 Eco1.User user hide)
(43 Eco2.User user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(44 Edge.Cuts user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(45 Margin user hide)
(46 B.CrtYd user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
(47 F.CrtYd user)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(48 B.Fab user hide)
(49 F.Fab user hide)
start pcb layout
2018-08-26 19:54:32 +00:00
)
(setup
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(last_trace_width 0.35)
(trace_clearance 0.15)
start pcb layout
2018-08-26 19:54:32 +00:00
(zone_clearance 0.508)
(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
add ground and power planes
2018-08-28 21:14:49 +00:00
(edge_width 0.2)
start pcb layout
2018-08-26 19:54:32 +00:00
(via_size 0.8)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via_drill 0.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 1.524 1.524)
(pad_drill 0.762)
(pad_to_mask_clearance 0.2)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
(layerselection 0x010fc_ffffffff)
(usegerberextensions false)
(usegerberattributes false)
(usegerberadvancedattributes false)
(creategerberjobfile false)
(excludeedgelayer true)
(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
(padsonsilk false)
(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
(drillshape 1)
(scaleselection 1)
(outputdirectory ""))
)
(net 0 "")
(net 1 +3V3)
(net 2 GND)
(net 3 GNDPWR)
(net 4 +24V)
(net 5 "Net-(D1-Pad1)")
(net 6 "Net-(D1-Pad2)")
(net 7 "Net-(D2-Pad2)")
(net 8 "Net-(D2-Pad1)")
(net 9 "Net-(D3-Pad1)")
(net 10 "Net-(D3-Pad2)")
(net 11 "Net-(D4-Pad2)")
(net 12 "Net-(D4-Pad1)")
(net 13 "Net-(D5-Pad2)")
(net 14 "Net-(D5-Pad1)")
(net 15 "Net-(D6-Pad1)")
(net 16 "Net-(D6-Pad2)")
(net 17 "Net-(D7-Pad2)")
(net 18 "Net-(D7-Pad1)")
(net 19 "Net-(D8-Pad1)")
(net 20 "Net-(D8-Pad2)")
(net 21 "Net-(D9-Pad1)")
(net 22 "Net-(D9-Pad2)")
(net 23 "Net-(D10-Pad2)")
(net 24 "Net-(D10-Pad1)")
(net 25 "Net-(D11-Pad1)")
(net 26 "Net-(D11-Pad2)")
(net 27 "Net-(D12-Pad2)")
(net 28 "Net-(D12-Pad1)")
(net 29 "Net-(J1-Pad2)")
(net 30 "Net-(J2-Pad2)")
(net 31 "Net-(J3-Pad2)")
(net 32 "Net-(J4-Pad1)")
(net 33 "Net-(J4-Pad2)")
(net 34 "Net-(J4-Pad3)")
(net 35 "Net-(J4-Pad6)")
(net 36 "Net-(J4-Pad7)")
(net 37 "Net-(J4-Pad8)")
(net 38 "Net-(J5-Pad8)")
(net 39 "Net-(J5-Pad7)")
(net 40 "Net-(J5-Pad6)")
(net 41 "Net-(J5-Pad3)")
(net 42 "Net-(J5-Pad2)")
(net 43 "Net-(J5-Pad1)")
(net 44 MCP_CS)
(net 45 "Net-(J6-Pad2)")
(net 46 "Net-(J6-Pad4)")
(net 47 "Net-(J6-Pad6)")
(net 48 "Net-(J6-Pad8)")
(net 49 "Net-(J6-Pad10)")
(net 50 "Net-(J6-Pad12)")
(net 51 "Net-(J6-Pad14)")
(net 52 "Net-(J6-Pad16)")
(net 53 "Net-(Q1-Pad3)")
(net 54 "Net-(Q2-Pad3)")
(net 55 "Net-(Q3-Pad3)")
(net 56 "Net-(Q4-Pad3)")
(net 57 "Net-(Q5-Pad3)")
(net 58 "Net-(Q6-Pad3)")
(net 59 "Net-(Q7-Pad3)")
(net 60 "Net-(Q8-Pad3)")
(net 61 "Net-(Q9-Pad3)")
(net 62 "Net-(Q10-Pad3)")
(net 63 "Net-(Q11-Pad3)")
(net 64 "Net-(Q12-Pad3)")
(net 65 +5V)
(net 66 "Net-(R1-Pad2)")
(net 67 "Net-(R17-Pad1)")
(net 68 "Net-(R19-Pad1)")
(net 69 "Net-(R21-Pad1)")
(net 70 "Net-(R23-Pad1)")
(net 71 "Net-(R25-Pad1)")
(net 72 "Net-(R27-Pad1)")
(net 73 "Net-(R29-Pad1)")
(net 74 "Net-(R31-Pad1)")
(net 75 "Net-(R33-Pad1)")
(net 76 "Net-(R35-Pad1)")
(net 77 "Net-(R36-Pad1)")
(net 78 "Net-(R37-Pad1)")
(net 79 "Net-(TP1-Pad1)")
(net 80 "Net-(TP2-Pad1)")
(net 81 "Net-(TP3-Pad1)")
(net 82 "Net-(TP4-Pad1)")
(net 83 "Net-(TP5-Pad1)")
(net 84 "Net-(TP6-Pad1)")
(net 85 "Net-(TP7-Pad1)")
(net 86 "Net-(TP8-Pad1)")
(net 87 "Net-(TP9-Pad1)")
(net 88 "Net-(TP10-Pad1)")
(net 89 "Net-(TP11-Pad1)")
(net 90 "Net-(TP12-Pad1)")
(net 91 "Net-(TP13-Pad1)")
(net 92 "Net-(TP14-Pad1)")
(net 93 "Net-(TP15-Pad1)")
(net 94 "Net-(TP16-Pad1)")
(net 95 SCK)
(net 96 MOSI)
(net 97 MISO)
(net 98 "Net-(U1-Pad19)")
(net 99 "Net-(U1-Pad20)")
(net 100 "Net-(J7-Pad27)")
(net 101 "Net-(J7-Pad26)")
(net 102 "Net-(J7-Pad25)")
(net 103 "Net-(J7-Pad24)")
(net 104 "Net-(J7-Pad23)")
(net 105 "Net-(J7-Pad22)")
(net 106 "Net-(J7-Pad21)")
(net 107 "Net-(J7-Pad20)")
(net 108 "Net-(J7-Pad19)")
(net 109 "Net-(J7-Pad18)")
(net 110 "Net-(J7-Pad17)")
(net 111 "Net-(J7-Pad16)")
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 112 +12V)
start pcb layout
2018-08-26 19:54:32 +00:00
(net_class Default "This is the default net class."
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(clearance 0.15)
(trace_width 0.35)
start pcb layout
2018-08-26 19:54:32 +00:00
(via_dia 0.8)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via_drill 0.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(uvia_dia 0.3)
(uvia_drill 0.1)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(add_net +12V)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(add_net +24V)
start pcb layout
2018-08-26 19:54:32 +00:00
(add_net +5V)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(add_net GNDPWR)
start pcb layout
2018-08-26 19:54:32 +00:00
(add_net MCP_CS)
(add_net MISO)
(add_net MOSI)
(add_net "Net-(D1-Pad1)")
(add_net "Net-(D1-Pad2)")
(add_net "Net-(D10-Pad1)")
(add_net "Net-(D10-Pad2)")
(add_net "Net-(D11-Pad1)")
(add_net "Net-(D11-Pad2)")
(add_net "Net-(D12-Pad1)")
(add_net "Net-(D12-Pad2)")
(add_net "Net-(D2-Pad1)")
(add_net "Net-(D2-Pad2)")
(add_net "Net-(D3-Pad1)")
(add_net "Net-(D3-Pad2)")
(add_net "Net-(D4-Pad1)")
(add_net "Net-(D4-Pad2)")
(add_net "Net-(D5-Pad1)")
(add_net "Net-(D5-Pad2)")
(add_net "Net-(D6-Pad1)")
(add_net "Net-(D6-Pad2)")
(add_net "Net-(D7-Pad1)")
(add_net "Net-(D7-Pad2)")
(add_net "Net-(D8-Pad1)")
(add_net "Net-(D8-Pad2)")
(add_net "Net-(D9-Pad1)")
(add_net "Net-(D9-Pad2)")
(add_net "Net-(J1-Pad2)")
(add_net "Net-(J2-Pad2)")
(add_net "Net-(J3-Pad2)")
(add_net "Net-(J4-Pad1)")
(add_net "Net-(J4-Pad2)")
(add_net "Net-(J4-Pad3)")
(add_net "Net-(J4-Pad6)")
(add_net "Net-(J4-Pad7)")
(add_net "Net-(J4-Pad8)")
(add_net "Net-(J5-Pad1)")
(add_net "Net-(J5-Pad2)")
(add_net "Net-(J5-Pad3)")
(add_net "Net-(J5-Pad6)")
(add_net "Net-(J5-Pad7)")
(add_net "Net-(J5-Pad8)")
(add_net "Net-(J6-Pad10)")
(add_net "Net-(J6-Pad12)")
(add_net "Net-(J6-Pad14)")
(add_net "Net-(J6-Pad16)")
(add_net "Net-(J6-Pad2)")
(add_net "Net-(J6-Pad4)")
(add_net "Net-(J6-Pad6)")
(add_net "Net-(J6-Pad8)")
(add_net "Net-(J7-Pad16)")
(add_net "Net-(J7-Pad17)")
(add_net "Net-(J7-Pad18)")
(add_net "Net-(J7-Pad19)")
(add_net "Net-(J7-Pad20)")
(add_net "Net-(J7-Pad21)")
(add_net "Net-(J7-Pad22)")
(add_net "Net-(J7-Pad23)")
(add_net "Net-(J7-Pad24)")
(add_net "Net-(J7-Pad25)")
(add_net "Net-(J7-Pad26)")
(add_net "Net-(J7-Pad27)")
(add_net "Net-(Q1-Pad3)")
(add_net "Net-(Q10-Pad3)")
(add_net "Net-(Q11-Pad3)")
(add_net "Net-(Q12-Pad3)")
(add_net "Net-(Q2-Pad3)")
(add_net "Net-(Q3-Pad3)")
(add_net "Net-(Q4-Pad3)")
(add_net "Net-(Q5-Pad3)")
(add_net "Net-(Q6-Pad3)")
(add_net "Net-(Q7-Pad3)")
(add_net "Net-(Q8-Pad3)")
(add_net "Net-(Q9-Pad3)")
(add_net "Net-(R1-Pad2)")
(add_net "Net-(R17-Pad1)")
(add_net "Net-(R19-Pad1)")
(add_net "Net-(R21-Pad1)")
(add_net "Net-(R23-Pad1)")
(add_net "Net-(R25-Pad1)")
(add_net "Net-(R27-Pad1)")
(add_net "Net-(R29-Pad1)")
(add_net "Net-(R31-Pad1)")
(add_net "Net-(R33-Pad1)")
(add_net "Net-(R35-Pad1)")
(add_net "Net-(R36-Pad1)")
(add_net "Net-(R37-Pad1)")
(add_net "Net-(TP1-Pad1)")
(add_net "Net-(TP10-Pad1)")
(add_net "Net-(TP11-Pad1)")
(add_net "Net-(TP12-Pad1)")
(add_net "Net-(TP13-Pad1)")
(add_net "Net-(TP14-Pad1)")
(add_net "Net-(TP15-Pad1)")
(add_net "Net-(TP16-Pad1)")
(add_net "Net-(TP2-Pad1)")
(add_net "Net-(TP3-Pad1)")
(add_net "Net-(TP4-Pad1)")
(add_net "Net-(TP5-Pad1)")
(add_net "Net-(TP6-Pad1)")
(add_net "Net-(TP7-Pad1)")
(add_net "Net-(TP8-Pad1)")
(add_net "Net-(TP9-Pad1)")
(add_net "Net-(U1-Pad19)")
(add_net "Net-(U1-Pad20)")
(add_net SCK)
)
add ground and power planes
2018-08-28 21:14:49 +00:00
(net_class "Power 3v3" ""
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(clearance 0.15)
add ground and power planes
2018-08-28 21:14:49 +00:00
(trace_width 0.5)
(via_dia 0.8)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(via_drill 0.5)
add ground and power planes
2018-08-28 21:14:49 +00:00
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +3V3)
(add_net GND)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_SO:SOIC-28W_7.5x17.9mm_P1.27mm (layer F.Cu) (tedit 5A02F2D3) (tstamp 5BBA1EC9)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 182.88 93.98 90)
(descr "28-Lead Plastic Small Outline (SO) - Wide, 7.50 mm Body [SOIC] (see Microchip Packaging Specification 00000049BS.pdf)")
(tags "SOIC 1.27")
(path /5B9C3DF9)
(attr smd)
(fp_text reference U1 (at 0 -10.05 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MCP23S17 (at 0 10.05 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.75 -8.95) (end 3.75 -8.95) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 -8.95) (end 3.75 8.95) (layer F.Fab) (width 0.15))
(fp_line (start 3.75 8.95) (end -3.75 8.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.75 8.95) (end -3.75 -7.95) (layer F.Fab) (width 0.15))
(fp_line (start -3.75 -7.95) (end -2.75 -8.95) (layer F.Fab) (width 0.15))
(fp_line (start -5.95 -9.3) (end -5.95 9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.95 -9.3) (end 5.95 9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 -9.3) (end 5.95 -9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.95 9.3) (end 5.95 9.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.875 -9.125) (end -3.875 -8.875) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 -9.125) (end 3.875 -8.78) (layer F.SilkS) (width 0.15))
(fp_line (start 3.875 9.125) (end 3.875 8.78) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 9.125) (end -3.875 8.78) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -9.125) (end 3.875 -9.125) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 9.125) (end 3.875 9.125) (layer F.SilkS) (width 0.15))
(fp_line (start -3.875 -8.875) (end -5.7 -8.875) (layer F.SilkS) (width 0.15))
(pad 1 smd rect (at -4.7 -8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 90 "Net-(TP12-Pad1)"))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 2 smd rect (at -4.7 -6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 89 "Net-(TP11-Pad1)"))
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(pad 3 smd rect (at -4.7 -5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 88 "Net-(TP10-Pad1)"))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 4 smd rect (at -4.7 -4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 94 "Net-(TP16-Pad1)"))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 5 smd rect (at -4.7 -3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 91 "Net-(TP13-Pad1)"))
(pad 6 smd rect (at -4.7 -1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 92 "Net-(TP14-Pad1)"))
(pad 7 smd rect (at -4.7 -0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 93 "Net-(TP15-Pad1)"))
(pad 8 smd rect (at -4.7 0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 87 "Net-(TP9-Pad1)"))
(pad 9 smd rect (at -4.7 1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 1 +3V3))
(pad 10 smd rect (at -4.7 3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(pad 11 smd rect (at -4.7 4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 12 smd rect (at -4.7 5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 95 SCK))
(pad 13 smd rect (at -4.7 6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 96 MOSI))
(pad 14 smd rect (at -4.7 8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 97 MISO))
(pad 15 smd rect (at 4.7 8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 31 "Net-(J3-Pad2)"))
(pad 16 smd rect (at 4.7 6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 30 "Net-(J2-Pad2)"))
(pad 17 smd rect (at 4.7 5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 29 "Net-(J1-Pad2)"))
(pad 18 smd rect (at 4.7 4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 66 "Net-(R1-Pad2)"))
(pad 19 smd rect (at 4.7 3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 98 "Net-(U1-Pad19)"))
(pad 20 smd rect (at 4.7 1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 99 "Net-(U1-Pad20)"))
(pad 21 smd rect (at 4.7 0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 83 "Net-(TP5-Pad1)"))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 22 smd rect (at 4.7 -0.635 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 84 "Net-(TP6-Pad1)"))
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(pad 23 smd rect (at 4.7 -1.905 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 86 "Net-(TP8-Pad1)"))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 24 smd rect (at 4.7 -3.175 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 85 "Net-(TP7-Pad1)"))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 25 smd rect (at 4.7 -4.445 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 79 "Net-(TP1-Pad1)"))
(pad 26 smd rect (at 4.7 -5.715 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 80 "Net-(TP2-Pad1)"))
(pad 27 smd rect (at 4.7 -6.985 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 81 "Net-(TP3-Pad1)"))
(pad 28 smd rect (at 4.7 -8.255 90) (size 2 0.6) (layers F.Cu F.Paste F.Mask)
(net 82 "Net-(TP4-Pad1)"))
(model ${KISYS3DMOD}/Package_SO.3dshapes/SOIC-28W_7.5x17.9mm_P1.27mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module DIN41617:DIN41617_31_short (layer F.Cu) (tedit 5B85C041) (tstamp 5BBA24C2)
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(at 221.75 89.49 90)
(path /5C0C9A4A)
(fp_text reference J7 (at -43.25 -6 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x31 (at 40 -5.75 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 35 -1.25) (end 35 7.637659) (layer F.SilkS) (width 1))
(fp_line (start 30 -1.25) (end 30 7.632978) (layer F.SilkS) (width 1))
(fp_line (start 25 -1.25) (end 25 7.623112) (layer F.SilkS) (width 1))
(fp_line (start 20 -1.25) (end 20 7.670728) (layer F.SilkS) (width 1))
(fp_line (start 15 -1.25) (end 15 7.62879) (layer F.SilkS) (width 1))
(fp_line (start 10 -1.25) (end 10 7.655555) (layer F.SilkS) (width 1))
(fp_line (start 5 -1.25) (end 5 7.64877) (layer F.SilkS) (width 1))
(fp_line (start 0 -1.25) (end 0 7.62) (layer F.SilkS) (width 1))
(fp_line (start -5 -1.25) (end -5 7.64877) (layer F.SilkS) (width 1))
(fp_line (start -10 -1.25) (end -10 7.632709) (layer F.SilkS) (width 1))
(fp_line (start -15 -1.25) (end -15 7.623246) (layer F.SilkS) (width 1))
(fp_line (start -20 -1.25) (end -20 7.625591) (layer F.SilkS) (width 1))
(fp_line (start -25 -1.25) (end -25 7.623112) (layer F.SilkS) (width 1))
(fp_line (start -30 -1.25) (end -30 7.632978) (layer F.SilkS) (width 1))
(fp_line (start -35 -1.25) (end -35 7.620317) (layer F.SilkS) (width 1))
(fp_line (start -32.5 1.25) (end -32.5 7.664) (layer F.SilkS) (width 1))
(fp_line (start -22.5 1.25) (end -22.5 7.625933) (layer F.SilkS) (width 1))
(fp_line (start -12.5 1.25) (end -12.5 7.623138) (layer F.SilkS) (width 1))
(fp_line (start -2.5 1.25) (end -2.5 7.647728) (layer F.SilkS) (width 1))
(fp_line (start 7.5 1.25) (end 7.5 7.62113) (layer F.SilkS) (width 1))
(fp_line (start 17.5 1.25) (end 17.5 7.62615) (layer F.SilkS) (width 1))
(fp_line (start 27.5 1.25) (end 27.5 7.635178) (layer F.SilkS) (width 1))
(fp_line (start 37.5 1.25) (end 37.5 7.648195) (layer F.SilkS) (width 1))
(fp_line (start 32.5 1.25) (end 32.5 7.621037) (layer F.SilkS) (width 1))
(fp_line (start 22.5 1.25) (end 22.5 7.625933) (layer F.SilkS) (width 1))
(fp_line (start 12.5 1.25) (end 12.5 7.634835) (layer F.SilkS) (width 1))
(fp_line (start 2.5 1.25) (end 2.5 7.620125) (layer F.SilkS) (width 1))
(fp_line (start -7.5 1.25) (end -7.5 7.640784) (layer F.SilkS) (width 1))
(fp_line (start -17.5 1.25) (end -17.5 7.62615) (layer F.SilkS) (width 1))
(fp_line (start -27.5 1.25) (end -27.5 7.622983) (layer F.SilkS) (width 1))
(fp_line (start -37.5 1.25) (end -37.465 7.62) (layer F.SilkS) (width 1))
(fp_line (start -45.3 -4.75) (end -45.3 8.25) (layer F.CrtYd) (width 0.15))
(fp_line (start 45.3 -4.75) (end -45.3 -4.75) (layer F.CrtYd) (width 0.15))
(fp_line (start 45.3 8.25) (end 45.3 -4.75) (layer F.CrtYd) (width 0.15))
(fp_line (start -45.3 8.25) (end 45.3 8.25) (layer F.CrtYd) (width 0.15))
(pad "" np_thru_hole circle (at 42.5 3.75 90) (size 3 3) (drill 3) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -42.5 3.75 90) (size 3 3) (drill 3) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 37.5 1.25 90) (size 2.2 2.2) (drill 1.31) (layers *.Cu *.Mask)
(net 2 GND))
(pad 2 thru_hole circle (at 35 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 112 +12V))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 3 thru_hole circle (at 32.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 65 +5V))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 4 thru_hole circle (at 30 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 1 +3V3))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 5 thru_hole circle (at 27.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 45 "Net-(J6-Pad2)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 6 thru_hole circle (at 25 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 46 "Net-(J6-Pad4)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 7 thru_hole circle (at 22.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 47 "Net-(J6-Pad6)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 8 thru_hole circle (at 20 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 48 "Net-(J6-Pad8)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 9 thru_hole circle (at 17.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 49 "Net-(J6-Pad10)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 10 thru_hole circle (at 15 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 50 "Net-(J6-Pad12)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 11 thru_hole circle (at 12.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 51 "Net-(J6-Pad14)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 12 thru_hole circle (at 10 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 52 "Net-(J6-Pad16)"))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 13 thru_hole circle (at 7.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 95 SCK))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 14 thru_hole circle (at 5 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 96 MOSI))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 15 thru_hole circle (at 2.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(net 97 MISO))
change for new din 31pin connector with shorter silkscreen
2018-08-28 21:41:52 +00:00
(pad 16 thru_hole circle (at 0 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 111 "Net-(J7-Pad16)"))
(pad 17 thru_hole circle (at -2.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 110 "Net-(J7-Pad17)"))
(pad 18 thru_hole circle (at -5 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 109 "Net-(J7-Pad18)"))
(pad 19 thru_hole circle (at -7.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 108 "Net-(J7-Pad19)"))
(pad 20 thru_hole circle (at -10 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 107 "Net-(J7-Pad20)"))
(pad 21 thru_hole circle (at -12.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 106 "Net-(J7-Pad21)"))
(pad 22 thru_hole circle (at -15 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 105 "Net-(J7-Pad22)"))
(pad 23 thru_hole circle (at -17.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 104 "Net-(J7-Pad23)"))
(pad 24 thru_hole circle (at -20 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 103 "Net-(J7-Pad24)"))
(pad 25 thru_hole circle (at -22.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 102 "Net-(J7-Pad25)"))
(pad 26 thru_hole circle (at -25 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 101 "Net-(J7-Pad26)"))
(pad 27 thru_hole circle (at -27.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 100 "Net-(J7-Pad27)"))
(pad 28 thru_hole circle (at -30 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 29 thru_hole circle (at -32.5 1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 30 thru_hole circle (at -35 -1.25 90) (size 2.5 2.5) (drill 1.31) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 31 thru_hole circle (at -37.5 1.25 90) (size 2.5 2.5) (drill 1.5) (layers *.Cu *.Mask)
(net 3 GNDPWR))
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA1495)
route more pcb
2018-08-26 20:13:25 +00:00
(at 187.325 85.09 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BFDF8F4)
(attr smd)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference R1 (at 0 -1.43 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value 10k (at 0 1.43 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 smd roundrect (at -0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
route some more
2018-08-26 20:30:55 +00:00
(net 1 +3V3))
route more pcb
2018-08-26 20:13:25 +00:00
(pad 2 smd roundrect (at 0.7875 0 270) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 66 "Net-(R1-Pad2)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5BBA1E2B)
route more pcb
2018-08-26 20:13:25 +00:00
(at 185.42 101.6)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(path /5CA079CD)
(attr smd)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference C1 (at 0 -1.43) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value 100nF (at 0 1.43) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
route more pcb
2018-08-26 20:13:25 +00:00
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Capacitor_SMD:CP_Elec_6.3x5.2 (layer F.Cu) (tedit 5B3026A2) (tstamp 5BBA25CB)
route some more
2018-08-26 20:30:55 +00:00
(at 207.645 50.8 90)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "SMT capacitor, aluminium electrolytic, 6.3x5.2, United Chemi-Con ")
(tags "Capacitor Electrolytic")
(path /5CA07BF6)
(attr smd)
(fp_text reference C2 (at 0 -4.35 90) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 100µF (at 0 4.35 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.15 0) (layer F.Fab) (width 0.1))
(fp_line (start 3.3 -3.3) (end 3.3 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.3 -3.3) (end 3.3 -3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.3 3.3) (end 3.3 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -3.3 -2.3) (end -3.3 2.3) (layer F.Fab) (width 0.1))
(fp_line (start -3.3 -2.3) (end -2.3 -3.3) (layer F.Fab) (width 0.1))
(fp_line (start -3.3 2.3) (end -2.3 3.3) (layer F.Fab) (width 0.1))
(fp_line (start -2.704838 -1.33) (end -2.074838 -1.33) (layer F.Fab) (width 0.1))
(fp_line (start -2.389838 -1.645) (end -2.389838 -1.015) (layer F.Fab) (width 0.1))
(fp_line (start 3.41 3.41) (end 3.41 1.06) (layer F.SilkS) (width 0.12))
(fp_line (start 3.41 -3.41) (end 3.41 -1.06) (layer F.SilkS) (width 0.12))
(fp_line (start -2.345563 -3.41) (end 3.41 -3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -2.345563 3.41) (end 3.41 3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 2.345563) (end -3.41 1.06) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 -2.345563) (end -3.41 -1.06) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 -2.345563) (end -2.345563 -3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -3.41 2.345563) (end -2.345563 3.41) (layer F.SilkS) (width 0.12))
(fp_line (start -4.4375 -1.8475) (end -3.65 -1.8475) (layer F.SilkS) (width 0.12))
(fp_line (start -4.04375 -2.24125) (end -4.04375 -1.45375) (layer F.SilkS) (width 0.12))
(fp_line (start 3.55 -3.55) (end 3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 -1.05) (end 4.8 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.8 -1.05) (end 4.8 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.8 1.05) (end 3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.55 1.05) (end 3.55 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.4 3.55) (end 3.55 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -2.4 -3.55) (end 3.55 -3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 2.4) (end -2.4 3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 -2.4) (end -2.4 -3.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 -2.4) (end -3.55 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 1.05) (end -3.55 2.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.55 -1.05) (end -4.8 -1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.8 -1.05) (end -4.8 1.05) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.8 1.05) (end -3.55 1.05) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at -2.8 0 90) (size 3.5 1.6) (layers F.Cu F.Paste F.Mask)
(net 1 +3V3))
(pad 2 smd rect (at 2.8 0 90) (size 3.5 1.6) (layers F.Cu F.Paste F.Mask)
(net 2 GND))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/CP_Elec_6.3x5.2.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Capacitor_SMD:C_0603_1608Metric (layer F.Cu) (tedit 5B301BBE) (tstamp 5BBA2068)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(at 124.46 99.695)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags capacitor)
(path /5C0C7E69)
(attr smd)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(fp_text reference C3 (at 0 -1.43) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(fp_text value 100nF (at 0 1.43) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 3 GNDPWR))
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 4 +24V))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/C_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Capacitor_SMD:CP_Elec_10x10 (layer F.Cu) (tedit 5A841F9D) (tstamp 5BBA15CC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 83.82 90.17 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "SMT capacitor, aluminium electrolytic, 10x10, Nichicon ")
(tags "Capacitor Electrolytic")
(path /5C0C76F7)
(attr smd)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(fp_text reference C4 (at 0 -6.2 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(fp_text value 100µF (at 0 6.2 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 5 0) (layer F.Fab) (width 0.1))
(fp_line (start 5.15 -5.15) (end 5.15 5.15) (layer F.Fab) (width 0.1))
(fp_line (start -4.15 -5.15) (end 5.15 -5.15) (layer F.Fab) (width 0.1))
(fp_line (start -4.15 5.15) (end 5.15 5.15) (layer F.Fab) (width 0.1))
(fp_line (start -5.15 -4.15) (end -5.15 4.15) (layer F.Fab) (width 0.1))
(fp_line (start -5.15 -4.15) (end -4.15 -5.15) (layer F.Fab) (width 0.1))
(fp_line (start -5.15 4.15) (end -4.15 5.15) (layer F.Fab) (width 0.1))
(fp_line (start -4.558325 -1.7) (end -3.558325 -1.7) (layer F.Fab) (width 0.1))
(fp_line (start -4.058325 -2.2) (end -4.058325 -1.2) (layer F.Fab) (width 0.1))
(fp_line (start 5.26 5.26) (end 5.26 1.51) (layer F.SilkS) (width 0.12))
(fp_line (start 5.26 -5.26) (end 5.26 -1.51) (layer F.SilkS) (width 0.12))
(fp_line (start -4.195563 -5.26) (end 5.26 -5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -4.195563 5.26) (end 5.26 5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 4.195563) (end -5.26 1.51) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 -4.195563) (end -5.26 -1.51) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 -4.195563) (end -4.195563 -5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -5.26 4.195563) (end -4.195563 5.26) (layer F.SilkS) (width 0.12))
(fp_line (start -6.75 -2.76) (end -5.5 -2.76) (layer F.SilkS) (width 0.12))
(fp_line (start -6.125 -3.385) (end -6.125 -2.135) (layer F.SilkS) (width 0.12))
(fp_line (start 5.4 -5.4) (end 5.4 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4 -1.5) (end 6.25 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.25 -1.5) (end 6.25 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.25 1.5) (end 5.4 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.4 1.5) (end 5.4 5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.25 5.4) (end 5.4 5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -4.25 -5.4) (end 5.4 -5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 4.25) (end -4.25 5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 -4.25) (end -4.25 -5.4) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 -4.25) (end -5.4 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 1.5) (end -5.4 4.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.4 -1.5) (end -6.25 -1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.25 -1.5) (end -6.25 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -6.25 1.5) (end -5.4 1.5) (layer F.CrtYd) (width 0.05))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(fp_text user %R (at 0 0 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 1 smd rect (at -4 0 180) (size 4 2.5) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 4 +24V))
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(pad 2 smd rect (at 4 0 180) (size 4 2.5) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Capacitor_SMD.3dshapes/CP_Elec_10x10.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA1B93)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 125.73 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D69F)
(attr smd)
(fp_text reference D1 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 5 "Net-(D1-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 6 "Net-(D1-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA1F9B)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 120.65 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D6A5)
(attr smd)
(fp_text reference D2 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 7 "Net-(D2-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 8 "Net-(D2-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA213C)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 115.57 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D6AB)
(attr smd)
(fp_text reference D3 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 9 "Net-(D3-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 10 "Net-(D3-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA2106)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 110.49 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B98D6B1)
(attr smd)
(fp_text reference D4 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 11 "Net-(D4-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 12 "Net-(D4-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA1776)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 93.98 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9871BF)
(attr smd)
(fp_text reference D5 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 13 "Net-(D5-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(D5-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA10FE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.727498 88.9 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B987245)
(attr smd)
(fp_text reference D6 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 15 "Net-(D6-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 16 "Net-(D6-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA20D0)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 83.82 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9872A3)
(attr smd)
(fp_text reference D7 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 17 "Net-(D7-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 18 "Net-(D7-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA1134)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B987307)
(attr smd)
(fp_text reference D8 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 19 "Net-(D8-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 20 "Net-(D8-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA116A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 60.96 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937BB)
(attr smd)
(fp_text reference D9 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 21 "Net-(D9-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 22 "Net-(D9-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA1F65)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 55.88 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937C1)
(attr smd)
(fp_text reference D10 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 23 "Net-(D10-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 24 "Net-(D10-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA2922)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 50.8 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937C7)
(attr smd)
(fp_text reference D11 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 25 "Net-(D11-Pad1)"))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 26 "Net-(D11-Pad2)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module LED_SMD:LED_0805_2012Metric (layer F.Cu) (tedit 5B36C52C) (tstamp 5BBA209A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 144.78 45.72 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "LED SMD 0805 (2012 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: https://docs.google.com/spreadsheets/d/1BsfQQcO9C6DZCsRaXUlFlo91Tg2WpOkGARC1WS5S8t0/edit?usp=sharing), generated with kicad-footprint-generator")
(tags diode)
(path /5B9937CD)
(attr smd)
(fp_text reference D12 (at 0 -1.65 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LED (at 0 1.65 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.5 0.5) (thickness 0.08)))
)
(fp_line (start 1.68 0.95) (end -1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.68 -0.95) (end 1.68 0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 -0.95) (end 1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.68 0.95) (end -1.68 -0.95) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.685 0.96) (end 1 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start -1.685 -0.96) (end -1.685 0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 -0.96) (end -1.685 -0.96) (layer F.SilkS) (width 0.12))
(fp_line (start 1 0.6) (end 1 -0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 0.6) (end 1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -1 -0.3) (end -1 0.6) (layer F.Fab) (width 0.1))
(fp_line (start -0.7 -0.6) (end -1 -0.3) (layer F.Fab) (width 0.1))
(fp_line (start 1 -0.6) (end -0.7 -0.6) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 27 "Net-(D12-Pad2)"))
(pad 1 smd roundrect (at -0.9375 0 180) (size 0.975 1.4) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 28 "Net-(D12-Pad1)"))
(model ${KISYS3DMOD}/LED_SMD.3dshapes/LED_0805_2012Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA1B3F)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(at 179.705 47.117 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)")
(tags "Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left")
(path /5C938F53)
(attr smd)
route some more
2018-08-26 20:30:55 +00:00
(fp_text reference J1 (at 0 -4.87 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text value ADDR2 (at 0 4.87 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -3.81) (end 1.27 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -0.32 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -2.54 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.86) (end -2.54 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.22) (end -1.27 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 2.22) (end -2.54 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.22) (end -2.54 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.86) (end -1.27 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.32) (end 2.54 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -0.32) (end 2.54 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0.32) (end 1.27 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.87) (end 1.33 -0.76) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.3) (end -2.85 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end -1.33 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 3.3) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 0.76) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.78) (end -1.33 1.78) (layer F.SilkS) (width 0.12))
(fp_line (start -3.45 -4.35) (end -3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 4.35) (end 3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 4.35) (end 3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 -4.35) (end -3.45 -4.35) (layer F.CrtYd) (width 0.05))
route some more
2018-08-26 20:30:55 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(pad 1 smd rect (at -1.655 -2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
route some more
2018-08-26 20:30:55 +00:00
(pad 3 smd rect (at -1.655 2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
route some more
2018-08-26 20:30:55 +00:00
(pad 2 smd rect (at 1.655 0 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 29 "Net-(J1-Pad2)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA26A3)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(at 188.595 47.117 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)")
(tags "Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left")
(path /5C93924C)
(attr smd)
route some more
2018-08-26 20:30:55 +00:00
(fp_text reference J2 (at 0 -4.87 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text value ADDR1 (at 0 4.87 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 3.45 -4.35) (end -3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 4.35) (end 3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 4.35) (end 3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 -4.35) (end -3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.78) (end -1.33 1.78) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 0.76) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 3.3) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end -1.33 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.3) (end -2.85 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.87) (end 1.33 -0.76) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 2.54 0.32) (end 1.27 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -0.32) (end 2.54 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.32) (end 2.54 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.86) (end -1.27 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.22) (end -2.54 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 2.22) (end -2.54 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.22) (end -1.27 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.86) (end -2.54 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -2.54 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -0.32 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -3.81) (end 1.27 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
route some more
2018-08-26 20:30:55 +00:00
(pad 2 smd rect (at 1.655 0 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 30 "Net-(J2-Pad2)"))
route some more
2018-08-26 20:30:55 +00:00
(pad 3 smd rect (at -1.655 2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
route some more
2018-08-26 20:30:55 +00:00
(pad 1 smd rect (at -1.655 -2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA239D)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(at 197.485 47.117 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 1x03, 2.54mm pitch, single row, style 1 (pin 1 left)")
(tags "Surface mounted pin header SMD 1x03 2.54mm single row style1 pin1 left")
(path /5C9392FE)
(attr smd)
route some more
2018-08-26 20:30:55 +00:00
(fp_text reference J3 (at 0 -4.87 270) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(fp_text value ADDR0 (at 0 4.87 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.27 3.81) (end -1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -0.32 -3.81) (end 1.27 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 3.81) (end -1.27 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -0.32 -3.81) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -3.81) (end 1.27 3.81) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -2.86) (end -2.54 -2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.86) (end -2.54 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -2.22) (end -1.27 -2.22) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 2.22) (end -2.54 2.22) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.22) (end -2.54 2.86) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 2.86) (end -1.27 2.86) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -0.32) (end 2.54 -0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -0.32) (end 2.54 0.32) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0.32) (end 1.27 0.32) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 -3.87) (end 1.33 -3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 3.87) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 -3.87) (end 1.33 -0.76) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.3) (end -2.85 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -3.87) (end -1.33 -3.3) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 3.3) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 0.76) (end 1.33 3.87) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.78) (end -1.33 1.78) (layer F.SilkS) (width 0.12))
(fp_line (start -3.45 -4.35) (end -3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.45 4.35) (end 3.45 4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 4.35) (end 3.45 -4.35) (layer F.CrtYd) (width 0.05))
(fp_line (start 3.45 -4.35) (end -3.45 -4.35) (layer F.CrtYd) (width 0.05))
route some more
2018-08-26 20:30:55 +00:00
(fp_text user %R (at 0 0) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route some more
2018-08-26 20:30:55 +00:00
(pad 1 smd rect (at -1.655 -2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 1 +3V3))
route some more
2018-08-26 20:30:55 +00:00
(pad 3 smd rect (at -1.655 2.54 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 2 GND))
route some more
2018-08-26 20:30:55 +00:00
(pad 2 smd rect (at 1.655 0 270) (size 2.51 1) (layers F.Cu F.Paste F.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 31 "Net-(J3-Pad2)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x03_P2.54mm_Vertical_SMD_Pin1Left.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_RJ:RJ45_Amphenol_54602-x08_Horizontal (layer F.Cu) (tedit 5B103613) (tstamp 5BBA19FB)
start pcb layout
2018-08-26 19:54:32 +00:00
(at 83.82 102.87 270)
(descr "8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf)")
(tags RJ45)
(path /5B72E546)
(fp_text reference J4 (at 4.445 -5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 8P8C (at 4.445 4 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 4.445 2 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -4 0.5) (end -3.5 0) (layer F.SilkS) (width 0.12))
(fp_line (start -4 -0.5) (end -4 0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -3.5 0) (end -4 -0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -3.205 13.97) (end -3.205 -2.77) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 13.97) (end -3.205 13.97) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 -3.77) (end 12.095 13.97) (layer F.Fab) (width 0.12))
(fp_line (start -2.205 -3.77) (end 12.095 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start -3.205 -2.77) (end -2.205 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start -3.315 14.08) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end -3.315 -3.88) (layer F.SilkS) (width 0.12))
(fp_line (start -3.315 -3.88) (end -3.315 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start -3.71 -4.27) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.71 -4.27) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 14.47) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 14.47) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(pad "" np_thru_hole circle (at 10.16 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at -1.27 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad 1 thru_hole rect (at 0 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 32 "Net-(J4-Pad1)"))
(pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 33 "Net-(J4-Pad2)"))
(pad 3 thru_hole circle (at 2.54 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 34 "Net-(J4-Pad3)"))
(pad 4 thru_hole circle (at 3.81 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 5 thru_hole circle (at 5.08 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 6 thru_hole circle (at 6.35 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 35 "Net-(J4-Pad6)"))
(pad 7 thru_hole circle (at 7.62 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 36 "Net-(J4-Pad7)"))
(pad 8 thru_hole circle (at 8.89 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 37 "Net-(J4-Pad8)"))
(model ${KISYS3DMOD}/Connector_RJ.3dshapes/RJ45_Amphenol_54602-x08_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_RJ:RJ45_Amphenol_54602-x08_Horizontal (layer F.Cu) (tedit 5B103613) (tstamp 5BBA1929)
route some more
2018-08-26 20:30:55 +00:00
(at 83.82 68.58 270)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "8 Pol Shallow Latch Connector, Modjack, RJ45 (https://cdn.amphenol-icc.com/media/wysiwyg/files/drawing/c-bmj-0102.pdf)")
(tags RJ45)
(path /5B742CE5)
(fp_text reference J5 (at 4.445 -5 270) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 8P8C (at 4.445 4 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 12.6 14.47) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(fp_line (start 12.6 14.47) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.71 -4.27) (end -3.71 14.47) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.71 -4.27) (end 12.6 -4.27) (layer F.CrtYd) (width 0.05))
(fp_line (start -3.315 -3.88) (end -3.315 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end -3.315 -3.88) (layer F.SilkS) (width 0.12))
(fp_line (start 12.205 -3.88) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start -3.315 14.08) (end 12.205 14.08) (layer F.SilkS) (width 0.12))
(fp_line (start -3.205 -2.77) (end -2.205 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start -2.205 -3.77) (end 12.095 -3.77) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 -3.77) (end 12.095 13.97) (layer F.Fab) (width 0.12))
(fp_line (start 12.095 13.97) (end -3.205 13.97) (layer F.Fab) (width 0.12))
(fp_line (start -3.205 13.97) (end -3.205 -2.77) (layer F.Fab) (width 0.12))
(fp_line (start -3.5 0) (end -4 -0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -4 -0.5) (end -4 0.5) (layer F.SilkS) (width 0.12))
(fp_line (start -4 0.5) (end -3.5 0) (layer F.SilkS) (width 0.12))
(fp_text user %R (at 4.445 2 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 8 thru_hole circle (at 8.89 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 38 "Net-(J5-Pad8)"))
(pad 7 thru_hole circle (at 7.62 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 39 "Net-(J5-Pad7)"))
(pad 6 thru_hole circle (at 6.35 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 40 "Net-(J5-Pad6)"))
(pad 5 thru_hole circle (at 5.08 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 4 thru_hole circle (at 3.81 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 3 GNDPWR))
(pad 3 thru_hole circle (at 2.54 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 41 "Net-(J5-Pad3)"))
(pad 2 thru_hole circle (at 1.27 -2.54 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 42 "Net-(J5-Pad2)"))
(pad 1 thru_hole rect (at 0 0 270) (size 1.5 1.5) (drill 0.76) (layers *.Cu *.Mask)
(net 43 "Net-(J5-Pad1)"))
(pad "" np_thru_hole circle (at -1.27 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(pad "" np_thru_hole circle (at 10.16 6.35 270) (size 3.2 3.2) (drill 3.2) (layers *.Cu *.Mask))
(model ${KISYS3DMOD}/Connector_RJ.3dshapes/RJ45_Amphenol_54602-x08_Horizontal.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_2x08_P2.54mm_Vertical_SMD (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA17FC)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(at 201.93 69.85)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "surface-mounted straight pin header, 2x08, 2.54mm pitch, double rows")
(tags "Surface mounted pin header SMD 2x08 2.54mm double row")
(path /5C251F2C)
(attr smd)
(fp_text reference J6 (at 0 -11.22) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_02x08_Odd_Even (at 0 11.22) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 2.54 10.16) (end -2.54 10.16) (layer F.Fab) (width 0.1))
(fp_line (start -1.59 -10.16) (end 2.54 -10.16) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 10.16) (end -2.54 -9.21) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -9.21) (end -1.59 -10.16) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -10.16) (end 2.54 10.16) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -9.21) (end -3.6 -9.21) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -9.21) (end -3.6 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -8.57) (end -2.54 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -9.21) (end 3.6 -9.21) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -9.21) (end 3.6 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -8.57) (end 2.54 -8.57) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -6.67) (end -3.6 -6.67) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -6.67) (end -3.6 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -6.03) (end -2.54 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -6.67) (end 3.6 -6.67) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -6.67) (end 3.6 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -6.03) (end 2.54 -6.03) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -4.13) (end -3.6 -4.13) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -4.13) (end -3.6 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -3.49) (end -2.54 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -4.13) (end 3.6 -4.13) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -4.13) (end 3.6 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -3.49) (end 2.54 -3.49) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 -1.59) (end -3.6 -1.59) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -1.59) (end -3.6 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 -0.95) (end -2.54 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 -1.59) (end 3.6 -1.59) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -1.59) (end 3.6 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 -0.95) (end 2.54 -0.95) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 0.95) (end -3.6 0.95) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 0.95) (end -3.6 1.59) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 1.59) (end -2.54 1.59) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 0.95) (end 3.6 0.95) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 0.95) (end 3.6 1.59) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 1.59) (end 2.54 1.59) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 3.49) (end -3.6 3.49) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 3.49) (end -3.6 4.13) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 4.13) (end -2.54 4.13) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 3.49) (end 3.6 3.49) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 3.49) (end 3.6 4.13) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 4.13) (end 2.54 4.13) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 6.03) (end -3.6 6.03) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 6.03) (end -3.6 6.67) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 6.67) (end -2.54 6.67) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 6.03) (end 3.6 6.03) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 6.03) (end 3.6 6.67) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 6.67) (end 2.54 6.67) (layer F.Fab) (width 0.1))
(fp_line (start -2.54 8.57) (end -3.6 8.57) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 8.57) (end -3.6 9.21) (layer F.Fab) (width 0.1))
(fp_line (start -3.6 9.21) (end -2.54 9.21) (layer F.Fab) (width 0.1))
(fp_line (start 2.54 8.57) (end 3.6 8.57) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 8.57) (end 3.6 9.21) (layer F.Fab) (width 0.1))
(fp_line (start 3.6 9.21) (end 2.54 9.21) (layer F.Fab) (width 0.1))
(fp_line (start -2.6 -10.22) (end 2.6 -10.22) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 10.22) (end 2.6 10.22) (layer F.SilkS) (width 0.12))
(fp_line (start -4.04 -9.65) (end -2.6 -9.65) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -10.22) (end -2.6 -9.65) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -10.22) (end 2.6 -9.65) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 9.65) (end -2.6 10.22) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 9.65) (end 2.6 10.22) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -8.13) (end -2.6 -7.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -8.13) (end 2.6 -7.11) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -5.59) (end -2.6 -4.57) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -5.59) (end 2.6 -4.57) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -3.05) (end -2.6 -2.03) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -3.05) (end 2.6 -2.03) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 -0.51) (end -2.6 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 -0.51) (end 2.6 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 2.03) (end -2.6 3.05) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 2.03) (end 2.6 3.05) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 4.57) (end -2.6 5.59) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 4.57) (end 2.6 5.59) (layer F.SilkS) (width 0.12))
(fp_line (start -2.6 7.11) (end -2.6 8.13) (layer F.SilkS) (width 0.12))
(fp_line (start 2.6 7.11) (end 2.6 8.13) (layer F.SilkS) (width 0.12))
(fp_line (start -5.9 -10.7) (end -5.9 10.7) (layer F.CrtYd) (width 0.05))
(fp_line (start -5.9 10.7) (end 5.9 10.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.9 10.7) (end 5.9 -10.7) (layer F.CrtYd) (width 0.05))
(fp_line (start 5.9 -10.7) (end -5.9 -10.7) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd rect (at -2.525 -8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 2 smd rect (at 2.525 -8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 45 "Net-(J6-Pad2)"))
(pad 3 smd rect (at -2.525 -6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 4 smd rect (at 2.525 -6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 46 "Net-(J6-Pad4)"))
(pad 5 smd rect (at -2.525 -3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 6 smd rect (at 2.525 -3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 47 "Net-(J6-Pad6)"))
(pad 7 smd rect (at -2.525 -1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 8 smd rect (at 2.525 -1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 48 "Net-(J6-Pad8)"))
(pad 9 smd rect (at -2.525 1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 10 smd rect (at 2.525 1.27) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 49 "Net-(J6-Pad10)"))
(pad 11 smd rect (at -2.525 3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 12 smd rect (at 2.525 3.81) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 50 "Net-(J6-Pad12)"))
(pad 13 smd rect (at -2.525 6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 14 smd rect (at 2.525 6.35) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 51 "Net-(J6-Pad14)"))
(pad 15 smd rect (at -2.525 8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 44 MCP_CS))
(pad 16 smd rect (at 2.525 8.89) (size 3.15 1) (layers F.Cu F.Paste F.Mask)
(net 52 "Net-(J6-Pad16)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_2x08_P2.54mm_Vertical_SMD.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA126D)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 128.27)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B738E50)
(fp_text reference Q1 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 53 "Net-(Q1-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 35 "Net-(J4-Pad6)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA0F28)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 123.19)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B73B28F)
(fp_text reference Q2 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 34 "Net-(J4-Pad3)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 54 "Net-(Q2-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA0EDD)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 118.11)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B73B2EB)
(fp_text reference Q3 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 55 "Net-(Q3-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 33 "Net-(J4-Pad2)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA27D6)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 113.03)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741988)
(fp_text reference Q4 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 32 "Net-(J4-Pad1)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 56 "Net-(Q4-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA0E6E)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 96.52)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B74198E)
(fp_text reference Q5 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 57 "Net-(Q5-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 36 "Net-(J4-Pad7)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA2A22)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 91.44)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741994)
(fp_text reference Q6 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 37 "Net-(J4-Pad8)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 58 "Net-(Q6-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA2C62)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 86.36)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741B64)
(fp_text reference Q7 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 43 "Net-(J5-Pad1)"))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 59 "Net-(Q7-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA22DB)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 81.28)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B741B6A)
(fp_text reference Q8 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 3.135) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 60 "Net-(Q8-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 42 "Net-(J5-Pad2)"))
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA1360)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 63.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B74524C)
(fp_text reference Q9 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 38 "Net-(J5-Pad8)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 61 "Net-(Q9-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA1E67)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 58.42)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B745252)
(fp_text reference Q10 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 62 "Net-(Q10-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 39 "Net-(J5-Pad7)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5BB69736) (tstamp 5BBA18D9)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 109.22 53.34)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B745258)
(fp_text reference Q11 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 40 "Net-(J5-Pad6)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 63 "Net-(Q11-Pad3)"))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_TO_SOT_THT:TO-126-3_Vertical (layer F.Cu) (tedit 5AC8BA0D) (tstamp 5BBA2026)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 95.885 48.26)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "TO-126-3, Vertical, RM 2.54mm, see https://www.diodes.com/assets/Package-Files/TO126.pdf")
(tags "TO-126-3 Vertical RM 2.54mm")
(path /5B74525E)
(fp_text reference Q12 (at 2.54 -3.12) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Q_PNP_ECB (at 2.54 2.5) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 2.54 -3.12) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 6.79 -2.25) (end -1.71 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.79 1.5) (end 6.79 -2.25) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 1.5) (end 6.79 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.71 -2.25) (end -1.71 1.5) (layer F.CrtYd) (width 0.05))
(fp_line (start 4.141 0.54) (end 4.141 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 4.141 -2.12) (end 4.141 -0.54) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 1.05) (end 0.94 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start 0.94 -2.12) (end 0.94 -1.05) (layer F.SilkS) (width 0.12))
(fp_line (start 6.66 -2.12) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end -1.58 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 1.37) (end 6.66 1.37) (layer F.SilkS) (width 0.12))
(fp_line (start -1.58 -2.12) (end 6.66 -2.12) (layer F.SilkS) (width 0.12))
(fp_line (start 4.14 -2) (end 4.14 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 0.94 -2) (end 0.94 1.25) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 -2) (end -1.46 -2) (layer F.Fab) (width 0.1))
(fp_line (start 6.54 1.25) (end 6.54 -2) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 1.25) (end 6.54 1.25) (layer F.Fab) (width 0.1))
(fp_line (start -1.46 -2) (end -1.46 1.25) (layer F.Fab) (width 0.1))
(pad 3 thru_hole oval (at 5.08 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 64 "Net-(Q12-Pad3)"))
(pad 2 thru_hole oval (at 2.54 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(net 41 "Net-(J5-Pad3)"))
start pcb layout
2018-08-26 19:54:32 +00:00
(pad 1 thru_hole rect (at 0 0) (size 1.8 1.8) (drill 1) (layers *.Cu *.Mask)
(net 4 +24V))
(model ${KISYS3DMOD}/Package_TO_SOT_THT.3dshapes/TO-126-3_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA171D)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 125.73)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BBE0F70)
(attr smd)
(fp_text reference R2 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 5 "Net-(D1-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA13D2)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 120.65)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06A12)
(attr smd)
(fp_text reference R3 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 8 "Net-(D2-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA11BF)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 115.57)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06ACC)
(attr smd)
(fp_text reference R4 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 9 "Net-(D3-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2B48)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.6475 110.49)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06B88)
(attr smd)
(fp_text reference R5 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 12 "Net-(D4-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA1327)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 93.98)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06C3C)
(attr smd)
(fp_text reference R6 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 14 "Net-(D5-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2C29)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 88.9)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06CF2)
(attr smd)
(fp_text reference R7 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 15 "Net-(D6-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA28F0)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 83.82)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06DAA)
(attr smd)
(fp_text reference R8 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 18 "Net-(D7-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2B78)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.495 78.74)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06E64)
(attr smd)
(fp_text reference R9 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 19 "Net-(D8-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA241F)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 60.96)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06F20)
(attr smd)
(fp_text reference R10 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 21 "Net-(D9-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2BF9)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 55.88)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC06FDE)
(attr smd)
(fp_text reference R11 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 24 "Net-(D10-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA109C)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 50.8)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC0709E)
(attr smd)
(fp_text reference R12 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 25 "Net-(D11-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA11EF)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 150.3425 45.72)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BC07160)
(attr smd)
(fp_text reference R13 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 820 (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 2 GND))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 28 "Net-(D12-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2CA4)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 128.27)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA1F194)
(attr smd)
(fp_text reference R14 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 53 "Net-(Q1-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA10CC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 123.19)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA4049C)
(attr smd)
(fp_text reference R15 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 54 "Net-(Q2-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2D25)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 118.11)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40536)
(attr smd)
(fp_text reference R16 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 55 "Net-(Q3-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2761)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 125.73 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BDE0369)
(attr smd)
(fp_text reference R17 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 67 "Net-(R17-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA26F5)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 113.03)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA405D2)
(attr smd)
(fp_text reference R18 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 56 "Net-(Q4-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA13A2)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 120.65 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A65F)
(attr smd)
(fp_text reference R19 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 68 "Net-(R19-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA0FAC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 96.52)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40670)
(attr smd)
(fp_text reference R20 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 57 "Net-(Q5-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA297A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 115.57 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A72D)
(attr smd)
(fp_text reference R21 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 69 "Net-(R21-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA28AE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 91.44)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40710)
(attr smd)
(fp_text reference R22 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 58 "Net-(Q6-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA106C)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 110.49 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A801)
(attr smd)
(fp_text reference R23 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 70 "Net-(R23-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5BB69854) (tstamp 5BBA2173)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 86.36)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA407B2)
(attr smd)
(fp_text reference R24 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 59 "Net-(Q7-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA14F5)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 93.98 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A8CB)
(attr smd)
(fp_text reference R25 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 71 "Net-(R25-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA1975)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 81.28)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40856)
(attr smd)
(fp_text reference R26 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 60 "Net-(Q8-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA23EF)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 88.9 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0A99B)
(attr smd)
(fp_text reference R27 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 72 "Net-(R27-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA1BC7)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 63.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40900)
(attr smd)
(fp_text reference R28 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 61 "Net-(Q9-Pad3)"))
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA14C5)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 83.82 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AA69)
(attr smd)
(fp_text reference R29 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 73 "Net-(R29-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA162A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 58.42)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA409A8)
(attr smd)
(fp_text reference R30 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 62 "Net-(Q10-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA1D6E)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AB39)
(attr smd)
(fp_text reference R31 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 74 "Net-(R31-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2203)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 53.34)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40A52)
(attr smd)
(fp_text reference R32 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 63 "Net-(Q11-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA0FDC)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 60.96 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AC0F)
(attr smd)
(fp_text reference R33 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 75 "Net-(R33-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA2584)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 121.92 48.26)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BA40C02)
(attr smd)
(fp_text reference R34 (at 0 -1.43) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 10k (at 0 1.43) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 4 +24V))
(pad 2 smd roundrect (at 0.7875 0) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 64 "Net-(Q12-Pad3)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA165A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 55.88 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0ACE7)
(attr smd)
(fp_text reference R35 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 76 "Net-(R35-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA1AFE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 50.8 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0ADBD)
(attr smd)
(fp_text reference R36 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 77 "Net-(R36-Pad1)"))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Resistor_SMD:R_0603_1608Metric (layer F.Cu) (tedit 5B301BBD) (tstamp 5BBA168A)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 127 45.72 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Resistor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC_7351 nominal, (Body size source: http://www.tortai-tech.com/upload/download/2011102023233369053.pdf), generated with kicad-footprint-generator")
(tags resistor)
(path /5BE0AE95)
(attr smd)
(fp_text reference R37 (at 0 -1.43 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value 1k (at 0 1.43 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.8 0.4) (end -0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.8 -0.4) (end 0.8 -0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 -0.4) (end 0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start 0.8 0.4) (end -0.8 0.4) (layer F.Fab) (width 0.1))
(fp_line (start -0.162779 -0.51) (end 0.162779 -0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -0.162779 0.51) (end 0.162779 0.51) (layer F.SilkS) (width 0.12))
(fp_line (start -1.48 0.73) (end -1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.48 -0.73) (end 1.48 -0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 -0.73) (end 1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.48 0.73) (end -1.48 0.73) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 180) (layer F.Fab)
(effects (font (size 0.4 0.4) (thickness 0.06)))
)
(pad 1 smd roundrect (at -0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 78 "Net-(R37-Pad1)"))
(pad 2 smd roundrect (at 0.7875 0 180) (size 0.875 0.95) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.25)
(net 3 GNDPWR))
(model ${KISYS3DMOD}/Resistor_SMD.3dshapes/R_0603_1608Metric.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA1CD0)
route more pcb
2018-08-26 20:13:25 +00:00
(at 175.26 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BC8AA0E)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP1 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 79 "Net-(TP1-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA21CB)
route more pcb
2018-08-26 20:13:25 +00:00
(at 172.72 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BCC7A69)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP2 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 80 "Net-(TP2-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA281C)
route more pcb
2018-08-26 20:13:25 +00:00
(at 170.18 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BCC7AF5)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP3 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 81 "Net-(TP3-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA2876)
route more pcb
2018-08-26 20:13:25 +00:00
(at 167.64 78.74 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5BCC7B87)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text reference TP4 (at 0 -2.33 180) (layer F.SilkS)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
route more pcb
2018-08-26 20:13:25 +00:00
(fp_text user %R (at 0 0 270) (layer F.Fab)
start pcb layout
2018-08-26 19:54:32 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
route more pcb
2018-08-26 20:13:25 +00:00
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
start pcb layout
2018-08-26 19:54:32 +00:00
(net 82 "Net-(TP4-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA1010)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 48.26)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED4F4)
(fp_text reference TP5 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 83 "Net-(TP5-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA2795)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 53.34)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED456)
(fp_text reference TP6 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 84 "Net-(TP6-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA16BE)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 63.5)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED27C)
(fp_text reference TP7 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 85 "Net-(TP7-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA2453)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 58.42)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED310)
(fp_text reference TP8 (at 0 -2.33) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 86 "Net-(TP8-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA1D36)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 81.28 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED108)
(fp_text reference TP9 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 87 "Net-(TP9-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA1BFB)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 123.19 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECC75)
(fp_text reference TP10 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 88 "Net-(TP10-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA2AC8)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 118.11 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECD15)
(fp_text reference TP11 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 89 "Net-(TP11-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA29E1)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 113.03 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECD9F)
(fp_text reference TP12 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 90 "Net-(TP12-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA2729)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 96.52 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECE31)
(fp_text reference TP13 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 91 "Net-(TP13-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA2A8C)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 91.44 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECFCE)
(fp_text reference TP14 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 92 "Net-(TP14-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA12B3)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 86.36 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ED072)
(fp_text reference TP15 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 93 "Net-(TP15-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Connector_PinHeader_2.54mm:PinHeader_1x01_P2.54mm_Vertical (layer F.Cu) (tedit 59FED5CC) (tstamp 5BBA12EF)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 156.21 128.27 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "Through hole straight pin header, 1x01, 2.54mm pitch, single row")
(tags "Through hole pin header THT 1x01 2.54mm single row")
(path /5B7ECA8C)
(fp_text reference TP16 (at 0 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value TestPoint (at 0 2.33 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 0 0 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 1.8 -1.8) (end -1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start 1.8 1.8) (end 1.8 -1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 1.8) (end 1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.8 -1.8) (end -1.8 1.8) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.33 -1.33) (end 0 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 0) (end -1.33 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end 1.33 1.27) (layer F.SilkS) (width 0.12))
(fp_line (start 1.33 1.27) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.27) (end -1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.33 1.33) (end 1.33 1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.27 -0.635) (end -0.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start -1.27 1.27) (end -1.27 -0.635) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 1.27) (end -1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start 1.27 -1.27) (end 1.27 1.27) (layer F.Fab) (width 0.1))
(fp_line (start -0.635 -1.27) (end 1.27 -1.27) (layer F.Fab) (width 0.1))
(pad 1 thru_hole rect (at 0 0 180) (size 1.7 1.7) (drill 1) (layers *.Cu *.Mask)
(net 94 "Net-(TP16-Pad1)"))
(model ${KISYS3DMOD}/Connector_PinHeader_2.54mm.3dshapes/PinHeader_1x01_P2.54mm_Vertical.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5BBA1538)
start pcb layout
2018-08-26 19:54:32 +00:00
(at 139.7 128.27 180)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5B7353E2)
(fp_text reference U2 (at 3.81 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-847 (at 3.81 20.11 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text user %R (at 3.81 8.89 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 53 "Net-(Q1-Pad3)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 11 "Net-(D4-Pad2)"))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 67 "Net-(R17-Pad1)"))
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 90 "Net-(TP12-Pad1)"))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 54 "Net-(Q2-Pad3)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 10 "Net-(D3-Pad2)"))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 68 "Net-(R19-Pad1)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 89 "Net-(TP11-Pad1)"))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 55 "Net-(Q3-Pad3)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 7 "Net-(D2-Pad2)"))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 69 "Net-(R21-Pad1)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 88 "Net-(TP10-Pad1)"))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 56 "Net-(Q4-Pad3)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 6 "Net-(D1-Pad2)"))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 70 "Net-(R23-Pad1)"))
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 94 "Net-(TP16-Pad1)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5BBA1DB1)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(at 139.7 96.52 180)
start pcb layout
2018-08-26 19:54:32 +00:00
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5B733EB2)
(fp_text reference U3 (at 3.81 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-847 (at 3.81 20.11 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 91 "Net-(TP13-Pad1)"))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 74 "Net-(R31-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 13 "Net-(D5-Pad2)"))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 60 "Net-(Q8-Pad3)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 92 "Net-(TP14-Pad1)"))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 73 "Net-(R29-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 16 "Net-(D6-Pad2)"))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 59 "Net-(Q7-Pad3)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 93 "Net-(TP15-Pad1)"))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 72 "Net-(R27-Pad1)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 17 "Net-(D7-Pad2)"))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 58 "Net-(Q6-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 87 "Net-(TP9-Pad1)"))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 71 "Net-(R25-Pad1)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 20 "Net-(D8-Pad2)"))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 57 "Net-(Q5-Pad3)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(module Package_DIP:DIP-16_W7.62mm (layer F.Cu) (tedit 5A02E8C5) (tstamp 5BBA263C)
start pcb layout
2018-08-26 19:54:32 +00:00
(at 139.7 63.5 180)
(descr "16-lead though-hole mounted DIP package, row spacing 7.62 mm (300 mils)")
(tags "THT DIP DIL PDIP 2.54mm 7.62mm 300mil")
(path /5B745234)
(fp_text reference U4 (at 3.81 -2.33 180) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value LTV-847 (at 3.81 20.11 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_arc (start 3.81 -1.33) (end 2.81 -1.33) (angle -180) (layer F.SilkS) (width 0.12))
(fp_line (start 1.635 -1.27) (end 6.985 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 -1.27) (end 6.985 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 6.985 19.05) (end 0.635 19.05) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 19.05) (end 0.635 -0.27) (layer F.Fab) (width 0.1))
(fp_line (start 0.635 -0.27) (end 1.635 -1.27) (layer F.Fab) (width 0.1))
(fp_line (start 2.81 -1.33) (end 1.16 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 -1.33) (end 1.16 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 1.16 19.11) (end 6.46 19.11) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 19.11) (end 6.46 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start 6.46 -1.33) (end 4.81 -1.33) (layer F.SilkS) (width 0.12))
(fp_line (start -1.1 -1.55) (end -1.1 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start -1.1 19.3) (end 8.7 19.3) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 19.3) (end 8.7 -1.55) (layer F.CrtYd) (width 0.05))
(fp_line (start 8.7 -1.55) (end -1.1 -1.55) (layer F.CrtYd) (width 0.05))
(fp_text user %R (at 3.81 8.89 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole rect (at 0 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 85 "Net-(TP7-Pad1)"))
(pad 9 thru_hole oval (at 7.62 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 78 "Net-(R37-Pad1)"))
(pad 2 thru_hole oval (at 0 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 22 "Net-(D9-Pad2)"))
(pad 10 thru_hole oval (at 7.62 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 64 "Net-(Q12-Pad3)"))
(pad 3 thru_hole oval (at 0 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 86 "Net-(TP8-Pad1)"))
(pad 11 thru_hole oval (at 7.62 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 77 "Net-(R36-Pad1)"))
(pad 4 thru_hole oval (at 0 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 23 "Net-(D10-Pad2)"))
(pad 12 thru_hole oval (at 7.62 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 63 "Net-(Q11-Pad3)"))
(pad 5 thru_hole oval (at 0 10.16 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 84 "Net-(TP6-Pad1)"))
(pad 13 thru_hole oval (at 7.62 7.62 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 76 "Net-(R35-Pad1)"))
(pad 6 thru_hole oval (at 0 12.7 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 26 "Net-(D11-Pad2)"))
(pad 14 thru_hole oval (at 7.62 5.08 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 62 "Net-(Q10-Pad3)"))
(pad 7 thru_hole oval (at 0 15.24 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 83 "Net-(TP5-Pad1)"))
(pad 15 thru_hole oval (at 7.62 2.54 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 75 "Net-(R33-Pad1)"))
(pad 8 thru_hole oval (at 0 17.78 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 27 "Net-(D12-Pad2)"))
(pad 16 thru_hole oval (at 7.62 0 180) (size 1.6 1.6) (drill 0.8) (layers *.Cu *.Mask)
(net 61 "Net-(Q9-Pad3)"))
(model ${KISYS3DMOD}/Package_DIP.3dshapes/DIP-16_W7.62mm.wrl
(at (xyz 0 0 0))
(scale (xyz 1 1 1))
(rotate (xyz 0 0 0))
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(gr_text "pneumatik ventil-io\n(c) Philipp Kramer\nRev. 2018-01" (at 187.96 124.46) (layer F.SilkS) (tstamp 5BBA2860)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(gr_line (start 70 140) (end 70 40) (layer Edge.Cuts) (width 0.2) (tstamp 5BBA285D))
(gr_line (start 230 140) (end 70 140) (layer Edge.Cuts) (width 0.2) (tstamp 5BBA285A))
(gr_line (start 230 40) (end 230 140) (layer Edge.Cuts) (width 0.2) (tstamp 5BBA2857))
(gr_line (start 70 40) (end 230 40) (layer Edge.Cuts) (width 0.2) (tstamp 5BBA2854))
start pcb layout
2018-08-26 19:54:32 +00:00
add front panel mount screws
2018-10-07 15:00:25 +00:00
(segment (start 184.785 101.4475) (end 184.6325 101.6) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2851))
(segment (start 184.785 98.68) (end 184.785 101.4475) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA284E))
(segment (start 211.08 53.6) (end 207.645 53.6) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA284B))
(segment (start 216.97 59.49) (end 211.08 53.6) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2848))
(segment (start 220.5 59.49) (end 216.97 59.49) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2845))
(via (at 186.182 84.074) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 1) (tstamp 5BBA2A76))
(segment (start 184.785 97.98) (end 184.912 97.853) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A73))
(segment (start 184.785 98.68) (end 184.785 97.98) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A70))
(via (at 184.912 93.218) (size 0.8) (drill 0.5) (layers F.Cu B.Cu) (net 1) (tstamp 5BBA2A6D))
(segment (start 184.912 97.853) (end 184.912 93.218) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A6A))
(segment (start 206.345 53.6) (end 206.339 53.594) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A67))
(segment (start 207.645 53.6) (end 206.345 53.6) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A64))
(segment (start 206.339 53.594) (end 201.168 53.594) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A61))
(segment (start 200.025 45.847) (end 199.898 45.72) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A5E))
(segment (start 200.025 52.451) (end 200.025 45.847) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A5B))
(segment (start 200.025 43.707) (end 198.736 42.418) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A58))
(segment (start 200.025 45.462) (end 200.025 43.707) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA2A55))
(segment (start 182.245 43.307) (end 182.245 45.462) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA1E19))
(segment (start 183.134 42.418) (end 182.245 43.307) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA1E16))
(segment (start 191.262 43.58) (end 191.262 42.418) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA1E13))
(segment (start 191.135 43.707) (end 191.262 43.58) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA1E10))
(segment (start 191.135 45.462) (end 191.135 43.707) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA1E0D))
(segment (start 198.736 42.418) (end 191.262 42.418) (width 0.5) (layer F.Cu) (net 1) (tstamp 5BBA1E0A))
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(segment (start 139.7 63.5) (end 141.224 63.5) (width 0.35) (layer F.Cu) (net 85) (tstamp 5BBA1C87))
(segment (start 156.21 63.5) (end 141.224 63.5) (width 0.35) (layer F.Cu) (net 85) (tstamp 5BBA1C84))
(segment (start 141.224 63.5) (end 140.97 63.5) (width 0.35) (layer F.Cu) (net 85) (tstamp 5BBA1C81))
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(segment (start 159.385 81.28) (end 156.21 81.28) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA1198))
(segment (start 160.655 81.28) (end 159.385 81.28) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA1195))
(segment (start 183.515 94.615) (end 181.61 92.71) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA1192))
(segment (start 161.925 92.71) (end 161.29 92.075) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA118F))
(segment (start 161.29 92.075) (end 161.29 81.915) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA2296))
(segment (start 161.29 81.915) (end 160.655 81.28) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA2293))
(segment (start 183.515 98.68) (end 183.515 94.615) (width 0.35) (layer F.Cu) (net 87) (tstamp 5BBA2290))
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(segment (start 139.7 123.19) (end 154.94 123.19) (width 0.35) (layer F.Cu) (net 88) (tstamp 5BBA228A))
(segment (start 154.94 123.19) (end 156.21 123.19) (width 0.35) (layer F.Cu) (net 88) (tstamp 5BBA2284))
(segment (start 177.165 114.3) (end 177.165 111.125) (width 0.35) (layer F.Cu) (net 88) (tstamp 5BBA2281))
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(segment (start 175.895006 115.569994) (end 177.165 114.3) (width 0.35) (layer F.Cu) (net 88) (tstamp 5BBA227B))
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(segment (start 177.165 111.125) (end 177.165 98.68) (width 0.35) (layer F.Cu) (net 88) (tstamp 5BBA200B))
(segment (start 161.925006 115.569994) (end 175.895006 115.569994) (width 0.35) (layer F.Cu) (net 88) (tstamp 5BBA2008))
(segment (start 175.895 98.68) (end 175.895 111.125) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA2287))
(segment (start 139.7 118.11) (end 154.94 118.11) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA2005))
(segment (start 158.75 118.11) (end 159.385 117.475) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA2002))
(segment (start 156.21 118.11) (end 158.75 118.11) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FFF))
(segment (start 159.385 117.475) (end 159.385 115.57) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FFC))
(segment (start 159.385 115.57) (end 160.655 114.3) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FF9))
(segment (start 154.94 118.11) (end 156.21 118.11) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FF6))
(segment (start 160.655 114.3) (end 174.625 114.3) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FF3))
(segment (start 175.895 113.03) (end 175.895 111.125) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FF0))
(segment (start 174.625 114.3) (end 175.895 113.03) (width 0.35) (layer F.Cu) (net 89) (tstamp 5BBA1FED))
(segment (start 139.7 113.03) (end 154.94 113.03) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA1FEA))
(segment (start 157.41 113.03) (end 156.21 113.03) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA1FE7))
(segment (start 154.94 113.03) (end 156.21 113.03) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA2D10))
(segment (start 174.625 111.125) (end 174.625 98.68) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA2D0D))
(segment (start 156.14 113.03) (end 173.355 113.03) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA2D0A))
(segment (start 174.625 111.76) (end 174.625 111.125) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA2D07))
(segment (start 173.355 113.03) (end 174.625 111.76) (width 0.35) (layer F.Cu) (net 90) (tstamp 5BBA2D04))
(segment (start 154.94 96.52) (end 139.7 96.52) (width 0.35) (layer F.Cu) (net 91) (tstamp 5BBA2D01))
(segment (start 154.94 96.52) (end 156.21 96.52) (width 0.35) (layer F.Cu) (net 91) (tstamp 5BBA2CFE))
(segment (start 156.21 96.52) (end 179.07 96.52) (width 0.35) (layer F.Cu) (net 91) (tstamp 5BBA2CFB))
(segment (start 179.705 97.155) (end 179.705 98.68) (width 0.35) (layer F.Cu) (net 91) (tstamp 5BBA2CF8))
(segment (start 179.07 96.52) (end 179.705 97.155) (width 0.35) (layer F.Cu) (net 91) (tstamp 5BBA2CF5))
(segment (start 139.7 91.44) (end 154.94 91.44) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA2CF2))
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(segment (start 161.925 95.25) (end 180.34 95.25) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F51))
(segment (start 180.34 95.25) (end 180.975 95.885) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F4E))
(segment (start 154.94 91.44) (end 156.21 91.44) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F4B))
(segment (start 156.21 91.44) (end 158.115 91.44) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F48))
(segment (start 158.115 91.44) (end 158.75 92.075) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F45))
(segment (start 158.75 92.075) (end 158.75 94.615) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F42))
(segment (start 158.75 94.615) (end 159.385 95.25) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F3F))
(segment (start 159.385 95.25) (end 161.925 95.25) (width 0.35) (layer F.Cu) (net 92) (tstamp 5BBA1F3C))
(segment (start 154.94 86.36) (end 139.7 86.36) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA1F39))
(segment (start 154.94 86.36) (end 156.21 86.36) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA1F36))
(segment (start 158.75 86.36) (end 156.21 86.36) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA1F33))
(segment (start 159.385 86.36) (end 158.75 86.36) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA1F30))
(segment (start 182.245 95.25) (end 180.975 93.98) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA1F2D))
(segment (start 182.245 98.68) (end 182.245 95.25) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA1F2A))
(segment (start 180.975 93.98) (end 160.655 93.98) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA29CB))
(segment (start 160.655 93.98) (end 160.02 93.345) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA29C8))
(segment (start 160.02 86.995) (end 159.385 86.36) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA29C5))
(segment (start 160.02 93.345) (end 160.02 86.995) (width 0.35) (layer F.Cu) (net 93) (tstamp 5BBA29C2))
(segment (start 178.435 98.68) (end 178.435 111.76) (width 0.35) (layer F.Cu) (net 94) (tstamp 5BBA2D13))
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(segment (start 160.02 128.27) (end 161.925 126.365) (width 0.35) (layer F.Cu) (net 94) (tstamp 5BBA29B6))
(segment (start 163.195 116.84) (end 177.165 116.84) (width 0.35) (layer F.Cu) (net 94) (tstamp 5BBA29B3))
(segment (start 177.165 116.84) (end 178.435 115.57) (width 0.35) (layer F.Cu) (net 94) (tstamp 5BBA29B0))
(segment (start 178.435 115.57) (end 178.435 111.76) (width 0.35) (layer F.Cu) (net 94) (tstamp 5BBA29AD))
(segment (start 223 81.99) (end 215.19 81.99) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA2968))
(segment (start 188.595 98.68) (end 188.595 95.25) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA2965))
(segment (start 198.755 93.98) (end 200.66 92.075) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA2962))
(segment (start 201.855 81.99) (end 215.19 81.99) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA295F))
(segment (start 188.595 95.25) (end 189.865 93.98) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA295C))
(segment (start 189.865 93.98) (end 198.755 93.98) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA2959))
(segment (start 200.66 83.185) (end 201.855 81.99) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA2956))
(segment (start 200.66 92.075) (end 200.66 83.185) (width 0.35) (layer F.Cu) (net 95) (tstamp 5BBA2953))
(segment (start 201.93 92.71) (end 201.93 85.725) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA2950))
(segment (start 220.5 84.49) (end 212.09 84.49) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA294D))
(segment (start 203.235 84.49) (end 212.09 84.49) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA294A))
(segment (start 212.09 84.49) (end 211.42 84.49) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA2947))
(segment (start 189.865 98.68) (end 189.865 96.520006) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA143B))
(segment (start 201.93 85.725) (end 203.2 84.455) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA1438))
(segment (start 189.865 96.520006) (end 191.135006 95.25) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA1435))
(segment (start 199.39 95.25) (end 201.93 92.71) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA1432))
(segment (start 203.2 84.455) (end 203.235 84.49) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA142F))
(segment (start 191.135006 95.25) (end 199.39 95.25) (width 0.35) (layer F.Cu) (net 96) (tstamp 5BBA142C))
(segment (start 191.135 97.155) (end 191.135 98.68) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA1429))
(segment (start 204.475 86.99) (end 203.2 88.265) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA1426))
(segment (start 203.2 88.265) (end 203.2 93.345) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA1423))
(segment (start 203.2 93.345) (end 200.025 96.52) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA1420))
(segment (start 191.77 96.52) (end 191.135 97.155) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA141D))
(segment (start 223 86.99) (end 204.475 86.99) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA141A))
(segment (start 200.025 96.52) (end 191.77 96.52) (width 0.35) (layer F.Cu) (net 97) (tstamp 5BBA1417))
start pcb layout
2018-08-26 19:54:32 +00:00
add front panel mount screws
2018-10-07 15:00:25 +00:00
(zone (net 3) (net_name GNDPWR) (layer B.Cu) (tstamp 5BBA1E4C) (hatch edge 0.508)
add ground and power planes
2018-08-28 21:14:49 +00:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
(xy 71.12 40.64) (xy 133.35 40.64) (xy 133.35 138.43) (xy 71.12 138.43)
)
)
(filled_polygon
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(xy 131.520091 44.36826) (xy 131.045423 44.685423) (xy 130.72826 45.160091) (xy 130.616887 45.72) (xy 130.72826 46.279909)
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(xy 130.616887 63.5) (xy 130.72826 64.059909) (xy 131.045423 64.534577) (xy 131.520091 64.85174) (xy 131.938667 64.935)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 132.221333 64.935) (xy 132.639909 64.85174) (xy 133.114577 64.534577) (xy 133.223 64.372311) (xy 133.223 77.867689)
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(xy 132.639909 97.87174) (xy 133.114577 97.554577) (xy 133.223 97.392311) (xy 133.223 109.617689) (xy 133.114577 109.455423)
add ground and power planes
2018-08-28 21:14:49 +00:00
(xy 132.639909 109.13826) (xy 132.221333 109.055) (xy 131.938667 109.055) (xy 131.520091 109.13826) (xy 131.045423 109.455423)
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finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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(xy 89.789 125.756643) (xy 89.789 125.871428) (xy 89.766608 125.984) (xy 71.247 125.984) (xy 71.247 112.585431)
add ground and power planes
2018-08-28 21:14:49 +00:00
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(xy 79.364741 111.763974) (xy 78.736026 111.135259) (xy 77.914569 110.795) (xy 77.025431 110.795) (xy 76.203974 111.135259)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 71.247 78.295431) (xy 75.235 78.295431) (xy 75.235 79.184569) (xy 75.575259 80.006026) (xy 76.203974 80.634741)
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(xy 79.705 78.295431) (xy 79.364741 77.473974) (xy 78.736026 76.845259) (xy 77.914569 76.505) (xy 77.025431 76.505)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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(xy 82.423 74.456555) (xy 82.423 73.459125) (xy 82.45077 74.005448) (xy 82.60754 74.383923) (xy 82.848483 74.451912)
add ground and power planes
2018-08-28 21:14:49 +00:00
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(xy 85.18923 73.314552) (xy 85.03246 72.936077) (xy 84.791517 72.868088) (xy 83.999605 73.66) (xy 83.640395 73.66)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(zone (net 3) (net_name GNDPWR) (layer F.Cu) (tstamp 5BBA2CC5) (hatch edge 0.508)
add ground and power planes
2018-08-28 21:14:49 +00:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
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)
)
(filled_polygon
(pts
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finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
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add front panel mount screws
2018-10-07 15:00:25 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
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increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
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add ground and power planes
2018-08-28 21:14:49 +00:00
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increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
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(xy 218.901974 98.422233) (xy 218.615 99.11505) (xy 218.615 99.86495) (xy 218.901974 100.557767) (xy 219.432233 101.088026)
(xy 220.12505 101.375) (xy 220.87495 101.375) (xy 221.284741 101.205259) (xy 221.115 101.61505) (xy 221.115 102.36495)
(xy 221.284741 102.774741) (xy 220.87495 102.605) (xy 220.12505 102.605) (xy 219.432233 102.891974) (xy 218.901974 103.422233)
(xy 218.615 104.11505) (xy 218.615 104.86495) (xy 218.901974 105.557767) (xy 219.432233 106.088026) (xy 220.12505 106.375)
(xy 220.87495 106.375) (xy 221.284741 106.205259) (xy 221.115 106.61505) (xy 221.115 107.36495) (xy 221.284741 107.774741)
(xy 220.87495 107.605) (xy 220.12505 107.605) (xy 219.432233 107.891974) (xy 218.901974 108.422233) (xy 218.615 109.11505)
(xy 218.615 109.86495) (xy 218.901974 110.557767) (xy 219.432233 111.088026) (xy 220.12505 111.375) (xy 220.87495 111.375)
(xy 221.284741 111.205259) (xy 221.115 111.61505) (xy 221.115 112.36495) (xy 221.284741 112.774741) (xy 220.87495 112.605)
(xy 220.12505 112.605) (xy 219.432233 112.891974) (xy 218.901974 113.422233) (xy 218.615 114.11505) (xy 218.615 114.86495)
(xy 218.901974 115.557767) (xy 219.432233 116.088026) (xy 220.12505 116.375) (xy 220.87495 116.375) (xy 221.284741 116.205259)
(xy 221.115 116.61505) (xy 221.115 116.713) (xy 210.82 116.713) (xy 210.771399 116.722667) (xy 210.730197 116.750197)
(xy 195.527394 131.953) (xy 138.557 131.953) (xy 138.557 129.604523) (xy 138.652235 129.668157) (xy 138.9 129.71744)
(xy 140.5 129.71744) (xy 140.747765 129.668157) (xy 140.957809 129.527809) (xy 141.098157 129.317765) (xy 141.14744 129.07)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 141.14744 127.47) (xy 141.137495 127.42) (xy 154.71256 127.42) (xy 154.71256 129.12) (xy 154.761843 129.367765)
(xy 154.902191 129.577809) (xy 155.112235 129.718157) (xy 155.36 129.76744) (xy 157.06 129.76744) (xy 157.307765 129.718157)
(xy 157.517809 129.577809) (xy 157.658157 129.367765) (xy 157.70744 129.12) (xy 157.70744 127.42) (xy 157.658157 127.172235)
(xy 157.517809 126.962191) (xy 157.307765 126.821843) (xy 157.06 126.77256) (xy 155.36 126.77256) (xy 155.112235 126.821843)
(xy 154.902191 126.962191) (xy 154.761843 127.172235) (xy 154.71256 127.42) (xy 141.137495 127.42) (xy 141.098157 127.222235)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 140.957809 127.012191) (xy 140.747765 126.871843) (xy 140.613894 126.845215) (xy 140.734577 126.764577) (xy 141.05174 126.289909)
(xy 141.163113 125.73) (xy 141.05174 125.170091) (xy 140.734577 124.695423) (xy 140.382242 124.46) (xy 140.734577 124.224577)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 141.05174 123.749909) (xy 141.163113 123.19) (xy 141.05174 122.630091) (xy 140.857908 122.34) (xy 154.71256 122.34)
(xy 154.71256 124.04) (xy 154.761843 124.287765) (xy 154.902191 124.497809) (xy 155.112235 124.638157) (xy 155.36 124.68744)
(xy 157.06 124.68744) (xy 157.307765 124.638157) (xy 157.517809 124.497809) (xy 157.658157 124.287765) (xy 157.70744 124.04)
(xy 157.70744 122.34) (xy 157.658157 122.092235) (xy 157.517809 121.882191) (xy 157.307765 121.741843) (xy 157.06 121.69256)
(xy 155.36 121.69256) (xy 155.112235 121.741843) (xy 154.902191 121.882191) (xy 154.761843 122.092235) (xy 154.71256 122.34)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 140.857908 122.34) (xy 140.734577 122.155423) (xy 140.382242 121.92) (xy 140.734577 121.684577) (xy 141.05174 121.209909)
(xy 141.163113 120.65) (xy 141.05174 120.090091) (xy 140.734577 119.615423) (xy 140.382242 119.38) (xy 140.734577 119.144577)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 141.05174 118.669909) (xy 141.163113 118.11) (xy 141.05174 117.550091) (xy 140.857908 117.26) (xy 154.71256 117.26)
(xy 154.71256 118.96) (xy 154.761843 119.207765) (xy 154.902191 119.417809) (xy 155.112235 119.558157) (xy 155.36 119.60744)
(xy 157.06 119.60744) (xy 157.307765 119.558157) (xy 157.517809 119.417809) (xy 157.658157 119.207765) (xy 157.70744 118.96)
(xy 157.70744 117.26) (xy 157.658157 117.012235) (xy 157.517809 116.802191) (xy 157.307765 116.661843) (xy 157.06 116.61256)
(xy 155.36 116.61256) (xy 155.112235 116.661843) (xy 154.902191 116.802191) (xy 154.761843 117.012235) (xy 154.71256 117.26)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 140.857908 117.26) (xy 140.734577 117.075423) (xy 140.382242 116.84) (xy 140.734577 116.604577) (xy 141.05174 116.129909)
(xy 141.163113 115.57) (xy 141.05174 115.010091) (xy 140.734577 114.535423) (xy 140.382242 114.3) (xy 140.734577 114.064577)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 141.05174 113.589909) (xy 141.163113 113.03) (xy 141.05174 112.470091) (xy 140.857908 112.18) (xy 154.71256 112.18)
(xy 154.71256 113.88) (xy 154.761843 114.127765) (xy 154.902191 114.337809) (xy 155.112235 114.478157) (xy 155.36 114.52744)
(xy 157.06 114.52744) (xy 157.307765 114.478157) (xy 157.517809 114.337809) (xy 157.658157 114.127765) (xy 157.70744 113.88)
(xy 157.70744 112.18) (xy 157.658157 111.932235) (xy 157.517809 111.722191) (xy 157.307765 111.581843) (xy 157.06 111.53256)
(xy 155.36 111.53256) (xy 155.112235 111.581843) (xy 154.902191 111.722191) (xy 154.761843 111.932235) (xy 154.71256 112.18)
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 140.857908 112.18) (xy 140.734577 111.995423) (xy 140.382242 111.76) (xy 140.734577 111.524577) (xy 141.05174 111.049909)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 141.163113 110.49) (xy 141.05174 109.930091) (xy 140.734577 109.455423) (xy 140.259909 109.13826) (xy 139.841333 109.055)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 139.558667 109.055) (xy 139.140091 109.13826) (xy 138.665423 109.455423) (xy 138.557 109.617689) (xy 138.557 97.854523)
(xy 138.652235 97.918157) (xy 138.9 97.96744) (xy 140.5 97.96744) (xy 140.747765 97.918157) (xy 140.957809 97.777809)
(xy 141.098157 97.567765) (xy 141.14744 97.32) (xy 141.14744 95.72) (xy 141.137495 95.67) (xy 154.71256 95.67)
(xy 154.71256 97.37) (xy 154.761843 97.617765) (xy 154.902191 97.827809) (xy 155.112235 97.968157) (xy 155.36 98.01744)
(xy 157.06 98.01744) (xy 157.307765 97.968157) (xy 157.517809 97.827809) (xy 157.658157 97.617765) (xy 157.70744 97.37)
(xy 157.70744 95.67) (xy 157.658157 95.422235) (xy 157.517809 95.212191) (xy 157.307765 95.071843) (xy 157.06 95.02256)
(xy 155.36 95.02256) (xy 155.112235 95.071843) (xy 154.902191 95.212191) (xy 154.761843 95.422235) (xy 154.71256 95.67)
(xy 141.137495 95.67) (xy 141.098157 95.472235) (xy 140.957809 95.262191) (xy 140.747765 95.121843) (xy 140.613894 95.095215)
(xy 140.734577 95.014577) (xy 141.05174 94.539909) (xy 141.163113 93.98) (xy 141.05174 93.420091) (xy 140.779147 93.012126)
(xy 183.877 93.012126) (xy 183.877 93.423874) (xy 184.034569 93.80428) (xy 184.32572 94.095431) (xy 184.706126 94.253)
(xy 185.117874 94.253) (xy 185.49828 94.095431) (xy 185.789431 93.80428) (xy 185.947 93.423874) (xy 185.947 93.012126)
(xy 185.797 92.649993) (xy 185.797 85.034804) (xy 185.976126 85.109) (xy 186.387874 85.109) (xy 186.76828 84.951431)
(xy 187.059431 84.66028) (xy 187.217 84.279874) (xy 187.217 83.868126) (xy 187.059431 83.48772) (xy 186.76828 83.196569)
(xy 186.387874 83.039) (xy 185.976126 83.039) (xy 185.797 83.113196) (xy 185.797 55.230578) (xy 186.548579 54.479)
(xy 199.583993 54.479) (xy 199.946126 54.629) (xy 200.357874 54.629) (xy 200.73828 54.471431) (xy 201.029431 54.18028)
(xy 201.187 53.799874) (xy 201.187 53.388126) (xy 201.029431 53.00772) (xy 200.73828 52.716569) (xy 200.357874 52.559)
(xy 199.946126 52.559) (xy 199.583993 52.709) (xy 186.269159 52.709) (xy 186.181999 52.691663) (xy 186.094839 52.709)
(xy 186.094835 52.709) (xy 185.83669 52.760348) (xy 185.836688 52.760349) (xy 185.836689 52.760349) (xy 185.617845 52.906576)
(xy 185.617844 52.906577) (xy 185.543951 52.955951) (xy 185.494577 53.029844) (xy 184.347845 54.176577) (xy 184.273952 54.225951)
(xy 184.224578 54.299844) (xy 184.224576 54.299846) (xy 184.078348 54.518691) (xy 184.009663 54.864) (xy 184.027001 54.951166)
(xy 184.027 83.986835) (xy 184.009662 84.074) (xy 184.027001 84.161169) (xy 184.027 92.649993) (xy 183.877 93.012126)
(xy 140.779147 93.012126) (xy 140.734577 92.945423) (xy 140.382242 92.71) (xy 140.734577 92.474577) (xy 141.05174 91.999909)
(xy 141.163113 91.44) (xy 141.05174 90.880091) (xy 140.857908 90.59) (xy 154.71256 90.59) (xy 154.71256 92.29)
(xy 154.761843 92.537765) (xy 154.902191 92.747809) (xy 155.112235 92.888157) (xy 155.36 92.93744) (xy 157.06 92.93744)
(xy 157.307765 92.888157) (xy 157.517809 92.747809) (xy 157.658157 92.537765) (xy 157.70744 92.29) (xy 157.70744 90.59)
(xy 157.658157 90.342235) (xy 157.517809 90.132191) (xy 157.307765 89.991843) (xy 157.06 89.94256) (xy 155.36 89.94256)
(xy 155.112235 89.991843) (xy 154.902191 90.132191) (xy 154.761843 90.342235) (xy 154.71256 90.59) (xy 140.857908 90.59)
(xy 140.734577 90.405423) (xy 140.382242 90.17) (xy 140.734577 89.934577) (xy 141.05174 89.459909) (xy 141.163113 88.9)
(xy 141.05174 88.340091) (xy 140.734577 87.865423) (xy 140.382242 87.63) (xy 140.734577 87.394577) (xy 141.05174 86.919909)
(xy 141.163113 86.36) (xy 141.05174 85.800091) (xy 140.857908 85.51) (xy 154.71256 85.51) (xy 154.71256 87.21)
(xy 154.761843 87.457765) (xy 154.902191 87.667809) (xy 155.112235 87.808157) (xy 155.36 87.85744) (xy 157.06 87.85744)
(xy 157.307765 87.808157) (xy 157.517809 87.667809) (xy 157.658157 87.457765) (xy 157.70744 87.21) (xy 157.70744 85.51)
(xy 157.658157 85.262235) (xy 157.517809 85.052191) (xy 157.307765 84.911843) (xy 157.06 84.86256) (xy 155.36 84.86256)
(xy 155.112235 84.911843) (xy 154.902191 85.052191) (xy 154.761843 85.262235) (xy 154.71256 85.51) (xy 140.857908 85.51)
(xy 140.734577 85.325423) (xy 140.382242 85.09) (xy 140.734577 84.854577) (xy 141.05174 84.379909) (xy 141.163113 83.82)
(xy 141.05174 83.260091) (xy 140.734577 82.785423) (xy 140.382242 82.55) (xy 140.734577 82.314577) (xy 141.05174 81.839909)
(xy 141.163113 81.28) (xy 141.05174 80.720091) (xy 140.857908 80.43) (xy 154.71256 80.43) (xy 154.71256 82.13)
(xy 154.761843 82.377765) (xy 154.902191 82.587809) (xy 155.112235 82.728157) (xy 155.36 82.77744) (xy 157.06 82.77744)
(xy 157.307765 82.728157) (xy 157.517809 82.587809) (xy 157.658157 82.377765) (xy 157.70744 82.13) (xy 157.70744 80.43)
(xy 157.658157 80.182235) (xy 157.517809 79.972191) (xy 157.307765 79.831843) (xy 157.06 79.78256) (xy 155.36 79.78256)
(xy 155.112235 79.831843) (xy 154.902191 79.972191) (xy 154.761843 80.182235) (xy 154.71256 80.43) (xy 140.857908 80.43)
(xy 140.734577 80.245423) (xy 140.382242 80.01) (xy 140.734577 79.774577) (xy 141.05174 79.299909) (xy 141.163113 78.74)
(xy 141.05174 78.180091) (xy 140.857908 77.89) (xy 166.14256 77.89) (xy 166.14256 79.59) (xy 166.191843 79.837765)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 166.332191 80.047809) (xy 166.542235 80.188157) (xy 166.79 80.23744) (xy 168.49 80.23744) (xy 168.737765 80.188157)
(xy 168.91 80.073072) (xy 169.082235 80.188157) (xy 169.33 80.23744) (xy 171.03 80.23744) (xy 171.277765 80.188157)
(xy 171.45 80.073072) (xy 171.622235 80.188157) (xy 171.87 80.23744) (xy 173.57 80.23744) (xy 173.817765 80.188157)
(xy 173.99 80.073072) (xy 174.162235 80.188157) (xy 174.41 80.23744) (xy 176.11 80.23744) (xy 176.357765 80.188157)
(xy 176.567809 80.047809) (xy 176.708157 79.837765) (xy 176.75744 79.59) (xy 176.75744 77.89) (xy 176.708157 77.642235)
(xy 176.567809 77.432191) (xy 176.357765 77.291843) (xy 176.11 77.24256) (xy 174.41 77.24256) (xy 174.162235 77.291843)
(xy 173.99 77.406928) (xy 173.817765 77.291843) (xy 173.57 77.24256) (xy 171.87 77.24256) (xy 171.622235 77.291843)
(xy 171.45 77.406928) (xy 171.277765 77.291843) (xy 171.03 77.24256) (xy 169.33 77.24256) (xy 169.082235 77.291843)
(xy 168.91 77.406928) (xy 168.737765 77.291843) (xy 168.49 77.24256) (xy 166.79 77.24256) (xy 166.542235 77.291843)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 166.332191 77.432191) (xy 166.191843 77.642235) (xy 166.14256 77.89) (xy 140.857908 77.89) (xy 140.734577 77.705423)
(xy 140.259909 77.38826) (xy 139.841333 77.305) (xy 139.558667 77.305) (xy 139.140091 77.38826) (xy 138.665423 77.705423)
(xy 138.557 77.867689) (xy 138.557 64.834523) (xy 138.652235 64.898157) (xy 138.9 64.94744) (xy 140.5 64.94744)
(xy 140.747765 64.898157) (xy 140.957809 64.757809) (xy 141.098157 64.547765) (xy 141.14744 64.3) (xy 141.14744 62.7)
(xy 141.137495 62.65) (xy 154.71256 62.65) (xy 154.71256 64.35) (xy 154.761843 64.597765) (xy 154.902191 64.807809)
(xy 155.112235 64.948157) (xy 155.36 64.99744) (xy 157.06 64.99744) (xy 157.307765 64.948157) (xy 157.517809 64.807809)
(xy 157.658157 64.597765) (xy 157.70744 64.35) (xy 157.70744 62.65) (xy 157.658157 62.402235) (xy 157.517809 62.192191)
(xy 157.307765 62.051843) (xy 157.06 62.00256) (xy 155.36 62.00256) (xy 155.112235 62.051843) (xy 154.902191 62.192191)
(xy 154.761843 62.402235) (xy 154.71256 62.65) (xy 141.137495 62.65) (xy 141.098157 62.452235) (xy 140.957809 62.242191)
(xy 140.747765 62.101843) (xy 140.613894 62.075215) (xy 140.734577 61.994577) (xy 141.05174 61.519909) (xy 141.163113 60.96)
(xy 141.05174 60.400091) (xy 140.734577 59.925423) (xy 140.382242 59.69) (xy 140.734577 59.454577) (xy 141.05174 58.979909)
(xy 141.163113 58.42) (xy 141.05174 57.860091) (xy 140.857908 57.57) (xy 154.71256 57.57) (xy 154.71256 59.27)
(xy 154.761843 59.517765) (xy 154.902191 59.727809) (xy 155.112235 59.868157) (xy 155.36 59.91744) (xy 157.06 59.91744)
(xy 157.307765 59.868157) (xy 157.517809 59.727809) (xy 157.658157 59.517765) (xy 157.70744 59.27) (xy 157.70744 57.57)
(xy 157.658157 57.322235) (xy 157.517809 57.112191) (xy 157.307765 56.971843) (xy 157.06 56.92256) (xy 155.36 56.92256)
(xy 155.112235 56.971843) (xy 154.902191 57.112191) (xy 154.761843 57.322235) (xy 154.71256 57.57) (xy 140.857908 57.57)
(xy 140.734577 57.385423) (xy 140.382242 57.15) (xy 140.734577 56.914577) (xy 141.05174 56.439909) (xy 141.163113 55.88)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 141.05174 55.320091) (xy 140.734577 54.845423) (xy 140.382242 54.61) (xy 140.734577 54.374577) (xy 141.05174 53.899909)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 141.163113 53.34) (xy 141.05174 52.780091) (xy 140.857908 52.49) (xy 154.71256 52.49) (xy 154.71256 54.19)
(xy 154.761843 54.437765) (xy 154.902191 54.647809) (xy 155.112235 54.788157) (xy 155.36 54.83744) (xy 157.06 54.83744)
(xy 157.307765 54.788157) (xy 157.517809 54.647809) (xy 157.658157 54.437765) (xy 157.70744 54.19) (xy 157.70744 52.49)
(xy 157.658157 52.242235) (xy 157.517809 52.032191) (xy 157.307765 51.891843) (xy 157.06 51.84256) (xy 155.36 51.84256)
(xy 155.112235 51.891843) (xy 154.902191 52.032191) (xy 154.761843 52.242235) (xy 154.71256 52.49) (xy 140.857908 52.49)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 140.734577 52.305423) (xy 140.382242 52.07) (xy 140.734577 51.834577) (xy 141.05174 51.359909) (xy 141.163113 50.8)
(xy 141.155891 50.763691) (xy 221.265 50.763691) (xy 221.265 51.70425) (xy 221.42375 51.863) (xy 222.873 51.863)
(xy 222.873 50.41375) (xy 223.127 50.41375) (xy 223.127 51.863) (xy 224.57625 51.863) (xy 224.735 51.70425)
(xy 224.735 50.763691) (xy 224.638327 50.530302) (xy 224.459699 50.351673) (xy 224.22631 50.255) (xy 223.28575 50.255)
(xy 223.127 50.41375) (xy 222.873 50.41375) (xy 222.71425 50.255) (xy 221.77369 50.255) (xy 221.540301 50.351673)
(xy 221.361673 50.530302) (xy 221.265 50.763691) (xy 141.155891 50.763691) (xy 141.05174 50.240091) (xy 140.734577 49.765423)
(xy 140.382242 49.53) (xy 140.734577 49.294577) (xy 141.05174 48.819909) (xy 141.163113 48.26) (xy 141.05174 47.700091)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 140.857908 47.41) (xy 154.71256 47.41) (xy 154.71256 49.11) (xy 154.761843 49.357765) (xy 154.902191 49.567809)
(xy 155.112235 49.708157) (xy 155.36 49.75744) (xy 157.06 49.75744) (xy 157.307765 49.708157) (xy 157.517809 49.567809)
(xy 157.658157 49.357765) (xy 157.70744 49.11) (xy 157.70744 47.41) (xy 157.658157 47.162235) (xy 157.517809 46.952191)
(xy 157.307765 46.811843) (xy 157.06 46.76256) (xy 155.36 46.76256) (xy 155.112235 46.811843) (xy 154.902191 46.952191)
(xy 154.761843 47.162235) (xy 154.71256 47.41) (xy 140.857908 47.41) (xy 140.734577 47.225423) (xy 140.382242 46.99)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
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(xy 138.557 40.767) (xy 228.473 40.767)
add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
)
add front panel mount screws
2018-10-07 15:00:25 +00:00
(zone (net 2) (net_name GND) (layer F.Cu) (tstamp 5BBA2161) (hatch edge 0.508)
add ground and power planes
2018-08-28 21:14:49 +00:00
(connect_pads (clearance 0.508))
(min_thickness 0.254)
(fill yes (arc_segments 16) (thermal_gap 0.508) (thermal_bridge_width 0.508))
(polygon
(pts
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
(xy 228.6 40.64) (xy 228.6 116.84) (xy 210.82 116.84) (xy 195.58 132.08) (xy 138.43 132.08)
(xy 138.43 40.64)
add ground and power planes
2018-08-28 21:14:49 +00:00
)
)
(filled_polygon
(pts
increase clearence for 24v rails
2018-09-11 21:02:17 +00:00
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finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 222.62505 60.105) (xy 222.215259 60.274741) (xy 222.385 59.86495) (xy 222.385 59.11505) (xy 222.215259 58.705259)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 222.62505 58.875) (xy 223.37495 58.875) (xy 224.067767 58.588026) (xy 224.598026 58.057767) (xy 224.885 57.36495)
(xy 224.885 56.61505) (xy 224.598026 55.922233) (xy 224.067767 55.391974) (xy 223.37495 55.105) (xy 222.62505 55.105)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 218.615 54.11505) (xy 218.615 54.86495) (xy 218.901974 55.557767) (xy 219.432233 56.088026) (xy 220.12505 56.375)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
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make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
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(xy 209.629773 65.23) (xy 209.55 65.214132) (xy 209.470227 65.23) (xy 206.586573 65.23) (xy 206.487809 65.082191)
(xy 206.277765 64.941843) (xy 206.03 64.89256) (xy 202.88 64.89256) (xy 202.632235 64.941843) (xy 202.422191 65.082191)
(xy 202.281843 65.292235) (xy 202.23256 65.54) (xy 202.23256 66.54) (xy 202.281843 66.787765) (xy 202.422191 66.997809)
(xy 202.632235 67.138157) (xy 202.88 67.18744) (xy 206.03 67.18744) (xy 206.277765 67.138157) (xy 206.487809 66.997809)
(xy 206.586573 66.85) (xy 209.214488 66.85) (xy 209.870834 67.506347) (xy 209.916023 67.573977) (xy 210.183954 67.753003)
(xy 210.420226 67.8) (xy 210.420227 67.8) (xy 210.5 67.815868) (xy 210.579773 67.8) (xy 219.654278 67.8)
(xy 219.432233 67.891974) (xy 218.901974 68.422233) (xy 218.795203 68.68) (xy 210.795512 68.68) (xy 210.179168 68.063656)
(xy 210.133977 67.996023) (xy 209.866046 67.816997) (xy 209.629774 67.77) (xy 209.629773 67.77) (xy 209.55 67.754132)
(xy 209.470227 67.77) (xy 206.586573 67.77) (xy 206.487809 67.622191) (xy 206.277765 67.481843) (xy 206.03 67.43256)
(xy 202.88 67.43256) (xy 202.632235 67.481843) (xy 202.422191 67.622191) (xy 202.281843 67.832235) (xy 202.23256 68.08)
(xy 202.23256 69.08) (xy 202.281843 69.327765) (xy 202.422191 69.537809) (xy 202.632235 69.678157) (xy 202.88 69.72744)
(xy 206.03 69.72744) (xy 206.277765 69.678157) (xy 206.487809 69.537809) (xy 206.586573 69.39) (xy 209.214488 69.39)
(xy 209.830832 70.006344) (xy 209.876023 70.073977) (xy 210.143954 70.253003) (xy 210.380226 70.3) (xy 210.38023 70.3)
(xy 210.459999 70.315867) (xy 210.539769 70.3) (xy 218.795203 70.3) (xy 218.901974 70.557767) (xy 219.432233 71.088026)
(xy 219.654278 71.18) (xy 210.755513 71.18) (xy 210.179168 70.603656) (xy 210.133977 70.536023) (xy 209.866046 70.356997)
(xy 209.629774 70.31) (xy 209.629773 70.31) (xy 209.55 70.294132) (xy 209.470227 70.31) (xy 206.586573 70.31)
(xy 206.487809 70.162191) (xy 206.277765 70.021843) (xy 206.03 69.97256) (xy 202.88 69.97256) (xy 202.632235 70.021843)
(xy 202.422191 70.162191) (xy 202.281843 70.372235) (xy 202.23256 70.62) (xy 202.23256 71.62) (xy 202.281843 71.867765)
(xy 202.422191 72.077809) (xy 202.632235 72.218157) (xy 202.88 72.26744) (xy 206.03 72.26744) (xy 206.277765 72.218157)
(xy 206.487809 72.077809) (xy 206.586573 71.93) (xy 209.214488 71.93) (xy 209.790834 72.506347) (xy 209.836023 72.573977)
(xy 209.903652 72.619165) (xy 210.103953 72.753003) (xy 210.42 72.815868) (xy 210.499774 72.8) (xy 219.654278 72.8)
(xy 219.432233 72.891974) (xy 218.901974 73.422233) (xy 218.795203 73.68) (xy 211.985513 73.68) (xy 211.449168 73.143656)
(xy 211.403977 73.076023) (xy 211.136046 72.896997) (xy 210.899774 72.85) (xy 210.899773 72.85) (xy 210.82 72.834132)
(xy 210.740227 72.85) (xy 206.586573 72.85) (xy 206.487809 72.702191) (xy 206.277765 72.561843) (xy 206.03 72.51256)
(xy 202.88 72.51256) (xy 202.632235 72.561843) (xy 202.422191 72.702191) (xy 202.281843 72.912235) (xy 202.23256 73.16)
(xy 202.23256 74.16) (xy 202.281843 74.407765) (xy 202.422191 74.617809) (xy 202.632235 74.758157) (xy 202.88 74.80744)
(xy 206.03 74.80744) (xy 206.277765 74.758157) (xy 206.487809 74.617809) (xy 206.586573 74.47) (xy 210.484488 74.47)
(xy 211.020834 75.006347) (xy 211.066023 75.073977) (xy 211.333954 75.253003) (xy 211.570226 75.3) (xy 211.649999 75.315868)
(xy 211.729772 75.3) (xy 218.795203 75.3) (xy 218.901974 75.557767) (xy 219.432233 76.088026) (xy 219.654278 76.18)
(xy 210.675513 76.18) (xy 210.179168 75.683656) (xy 210.133977 75.616023) (xy 209.866046 75.436997) (xy 209.629774 75.39)
(xy 209.629773 75.39) (xy 209.55 75.374132) (xy 209.470227 75.39) (xy 206.586573 75.39) (xy 206.487809 75.242191)
(xy 206.277765 75.101843) (xy 206.03 75.05256) (xy 202.88 75.05256) (xy 202.632235 75.101843) (xy 202.422191 75.242191)
(xy 202.281843 75.452235) (xy 202.23256 75.7) (xy 202.23256 76.7) (xy 202.281843 76.947765) (xy 202.422191 77.157809)
(xy 202.632235 77.298157) (xy 202.88 77.34744) (xy 206.03 77.34744) (xy 206.277765 77.298157) (xy 206.487809 77.157809)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 206.586573 77.01) (xy 209.214488 77.01) (xy 209.710834 77.506347) (xy 209.756023 77.573977) (xy 209.857592 77.641843)
make traces bigger and fix drc warnings
2018-09-11 21:24:05 +00:00
(xy 210.023953 77.753003) (xy 210.34 77.815868) (xy 210.419774 77.8) (xy 219.654278 77.8) (xy 219.432233 77.891974)
(xy 218.901974 78.422233) (xy 218.795203 78.68) (xy 209.365513 78.68) (xy 208.909168 78.223656) (xy 208.863977 78.156023)
(xy 208.596046 77.976997) (xy 208.359774 77.93) (xy 208.359773 77.93) (xy 208.28 77.914132) (xy 208.200227 77.93)
(xy 206.586573 77.93) (xy 206.487809 77.782191) (xy 206.277765 77.641843) (xy 206.03 77.59256) (xy 202.88 77.59256)
(xy 202.632235 77.641843) (xy 202.422191 77.782191) (xy 202.281843 77.992235) (xy 202.23256 78.24) (xy 202.23256 79.24)
(xy 202.281843 79.487765) (xy 202.422191 79.697809) (xy 202.632235 79.838157) (xy 202.88 79.88744) (xy 206.03 79.88744)
(xy 206.277765 79.838157) (xy 206.487809 79.697809) (xy 206.586573 79.55) (xy 207.944488 79.55) (xy 208.400834 80.006347)
(xy 208.446023 80.073977) (xy 208.713954 80.253003) (xy 208.950226 80.3) (xy 209.029999 80.315868) (xy 209.109772 80.3)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 218.795203 80.3) (xy 218.901974 80.557767) (xy 219.432233 81.088026) (xy 219.654278 81.18) (xy 201.934772 81.18)
(xy 201.854999 81.164132) (xy 201.775226 81.18) (xy 201.538954 81.226997) (xy 201.271023 81.406023) (xy 201.225834 81.473653)
(xy 200.215 82.484488) (xy 200.215 79.88744) (xy 200.98 79.88744) (xy 201.227765 79.838157) (xy 201.437809 79.697809)
(xy 201.578157 79.487765) (xy 201.62744 79.24) (xy 201.62744 78.24) (xy 201.578157 77.992235) (xy 201.437809 77.782191)
(xy 201.227765 77.641843) (xy 200.98 77.59256) (xy 200.215 77.59256) (xy 200.215 77.34744) (xy 200.98 77.34744)
(xy 201.227765 77.298157) (xy 201.437809 77.157809) (xy 201.578157 76.947765) (xy 201.62744 76.7) (xy 201.62744 75.7)
(xy 201.578157 75.452235) (xy 201.437809 75.242191) (xy 201.227765 75.101843) (xy 200.98 75.05256) (xy 200.215 75.05256)
(xy 200.215 74.80744) (xy 200.98 74.80744) (xy 201.227765 74.758157) (xy 201.437809 74.617809) (xy 201.578157 74.407765)
(xy 201.62744 74.16) (xy 201.62744 73.16) (xy 201.578157 72.912235) (xy 201.437809 72.702191) (xy 201.227765 72.561843)
(xy 200.98 72.51256) (xy 200.215 72.51256) (xy 200.215 72.26744) (xy 200.98 72.26744) (xy 201.227765 72.218157)
(xy 201.437809 72.077809) (xy 201.578157 71.867765) (xy 201.62744 71.62) (xy 201.62744 70.62) (xy 201.578157 70.372235)
(xy 201.437809 70.162191) (xy 201.227765 70.021843) (xy 200.98 69.97256) (xy 200.215 69.97256) (xy 200.215 69.72744)
(xy 200.98 69.72744) (xy 201.227765 69.678157) (xy 201.437809 69.537809) (xy 201.578157 69.327765) (xy 201.62744 69.08)
(xy 201.62744 68.08) (xy 201.578157 67.832235) (xy 201.437809 67.622191) (xy 201.227765 67.481843) (xy 200.98 67.43256)
(xy 200.215 67.43256) (xy 200.215 67.18744) (xy 200.98 67.18744) (xy 201.227765 67.138157) (xy 201.437809 66.997809)
(xy 201.578157 66.787765) (xy 201.62744 66.54) (xy 201.62744 65.54) (xy 201.578157 65.292235) (xy 201.437809 65.082191)
(xy 201.227765 64.941843) (xy 200.98 64.89256) (xy 200.215 64.89256) (xy 200.215 64.64744) (xy 200.98 64.64744)
(xy 201.227765 64.598157) (xy 201.437809 64.457809) (xy 201.578157 64.247765) (xy 201.62744 64) (xy 201.62744 63)
(xy 201.578157 62.752235) (xy 201.437809 62.542191) (xy 201.227765 62.401843) (xy 200.98 62.35256) (xy 200.215 62.35256)
(xy 200.215 62.10744) (xy 200.98 62.10744) (xy 201.227765 62.058157) (xy 201.437809 61.917809) (xy 201.578157 61.707765)
(xy 201.62744 61.46) (xy 201.62744 60.46) (xy 201.578157 60.212235) (xy 201.437809 60.002191) (xy 201.227765 59.861843)
(xy 200.98 59.81256) (xy 197.83 59.81256) (xy 197.582235 59.861843) (xy 197.372191 60.002191) (xy 197.231843 60.212235)
(xy 197.18256 60.46) (xy 197.18256 61.46) (xy 197.231843 61.707765) (xy 197.372191 61.917809) (xy 197.582235 62.058157)
(xy 197.83 62.10744) (xy 198.595 62.10744) (xy 198.595 62.35256) (xy 197.83 62.35256) (xy 197.582235 62.401843)
(xy 197.372191 62.542191) (xy 197.231843 62.752235) (xy 197.18256 63) (xy 197.18256 64) (xy 197.231843 64.247765)
(xy 197.372191 64.457809) (xy 197.582235 64.598157) (xy 197.83 64.64744) (xy 198.595 64.64744) (xy 198.595001 64.89256)
(xy 197.83 64.89256) (xy 197.582235 64.941843) (xy 197.372191 65.082191) (xy 197.231843 65.292235) (xy 197.18256 65.54)
(xy 197.18256 66.54) (xy 197.231843 66.787765) (xy 197.372191 66.997809) (xy 197.582235 67.138157) (xy 197.83 67.18744)
(xy 198.595 67.18744) (xy 198.595001 67.43256) (xy 197.83 67.43256) (xy 197.582235 67.481843) (xy 197.372191 67.622191)
(xy 197.231843 67.832235) (xy 197.18256 68.08) (xy 197.18256 69.08) (xy 197.231843 69.327765) (xy 197.372191 69.537809)
(xy 197.582235 69.678157) (xy 197.83 69.72744) (xy 198.595 69.72744) (xy 198.595001 69.97256) (xy 197.83 69.97256)
(xy 197.582235 70.021843) (xy 197.372191 70.162191) (xy 197.231843 70.372235) (xy 197.18256 70.62) (xy 197.18256 71.62)
(xy 197.231843 71.867765) (xy 197.372191 72.077809) (xy 197.582235 72.218157) (xy 197.83 72.26744) (xy 198.595 72.26744)
(xy 198.595001 72.51256) (xy 197.83 72.51256) (xy 197.582235 72.561843) (xy 197.372191 72.702191) (xy 197.231843 72.912235)
(xy 197.18256 73.16) (xy 197.18256 74.16) (xy 197.231843 74.407765) (xy 197.372191 74.617809) (xy 197.582235 74.758157)
(xy 197.83 74.80744) (xy 198.595 74.80744) (xy 198.595001 75.05256) (xy 197.83 75.05256) (xy 197.582235 75.101843)
(xy 197.372191 75.242191) (xy 197.231843 75.452235) (xy 197.18256 75.7) (xy 197.18256 76.7) (xy 197.231843 76.947765)
(xy 197.372191 77.157809) (xy 197.582235 77.298157) (xy 197.83 77.34744) (xy 198.595 77.34744) (xy 198.595 77.59256)
(xy 197.83 77.59256) (xy 197.582235 77.641843) (xy 197.372191 77.782191) (xy 197.231843 77.992235) (xy 197.18256 78.24)
(xy 197.18256 79.24) (xy 197.231843 79.487765) (xy 197.372191 79.697809) (xy 197.582235 79.838157) (xy 197.83 79.88744)
(xy 198.595 79.88744) (xy 198.595001 91.089486) (xy 197.784488 91.9) (xy 188.674772 91.9) (xy 188.594999 91.884132)
(xy 188.515226 91.9) (xy 188.278954 91.946997) (xy 188.011023 92.126023) (xy 187.965835 92.193652) (xy 186.808656 93.350832)
(xy 186.741023 93.396023) (xy 186.561997 93.663955) (xy 186.520018 93.875) (xy 186.499132 93.98) (xy 186.515 94.059773)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 186.515001 97.058955) (xy 186.48131 97.045) (xy 186.34075 97.045) (xy 186.182 97.20375) (xy 186.182 98.553)
(xy 186.202 98.553) (xy 186.202 98.807) (xy 186.182 98.807) (xy 186.182 100.15625) (xy 186.34075 100.315)
(xy 186.48131 100.315) (xy 186.698028 100.225232) (xy 186.777235 100.278157) (xy 187.025 100.32744) (xy 187.625 100.32744)
changed some positions and traces, TODO: change pin order on port expander and Optocouplers to reduce vias
2018-10-04 23:12:43 +00:00
(xy 187.872765 100.278157) (xy 187.96 100.219868) (xy 188.047235 100.278157) (xy 188.295 100.32744) (xy 188.895 100.32744)
(xy 189.142765 100.278157) (xy 189.23 100.219868) (xy 189.317235 100.278157) (xy 189.565 100.32744) (xy 190.165 100.32744)
(xy 190.412765 100.278157) (xy 190.5 100.219868) (xy 190.587235 100.278157) (xy 190.835 100.32744) (xy 191.435 100.32744)
(xy 191.682765 100.278157) (xy 191.892809 100.137809) (xy 192.033157 99.927765) (xy 192.08244 99.68) (xy 192.08244 97.68)
(xy 192.033157 97.432235) (xy 192.021189 97.414324) (xy 192.105513 97.33) (xy 199.945227 97.33) (xy 200.025 97.345868)
(xy 200.104773 97.33) (xy 200.104774 97.33) (xy 200.341046 97.283003) (xy 200.608977 97.103977) (xy 200.654168 97.036344)
finished new traces, added some GND via, changed polygons to be GND/GNDPWR
2018-10-05 18:20:09 +00:00
(xy 203.716347 93.974166) (xy 203.783977 93.928977) (xy 203.963003 93.661046) (xy 204.01 93.424774) (xy 204.01 93.424773)
(xy 204.025868 93.345001) (xy 204.01 93.265228) (xy 204.01 88.600512) (xy 204.810513 87.8) (xy 219.654278 87.8)
(xy 219.432233 87.891974) (xy 218.901974 88.422233) (xy 218.615 89.11505) (xy 218.615 89.86495) (xy 218.901974 90.557767)
(xy 219.432233 91.088026) (xy 220.12505 91.375) (xy 220.87495 91.375) (xy 221.284741 91.205259) (xy 221.115 91.61505)
(xy 221.115 92.36495) (xy 221.284741 92.774741) (xy 220.87495 92.605) (xy 220.12505 92.605) (xy 219.432233 92.891974)
(xy 218.901974 93.422233) (xy 218.615 94.11505) (xy 218.615 94.86495) (xy 218.901974 95.557767) (xy 219.432233 96.088026)
(xy 220.12505 96.375) (xy 220.87495 96.375) (xy 221.284741 96.205259) (xy 221.115 96.61505) (xy 221.115 97.36495)
(xy 221.284741 97.774741) (xy 220.87495 97.605) (xy 220.12505 97.605) (xy 219.432233 97.891974) (xy 218.901974 98.422233)
(xy 218.615 99.11505) (xy 218.615 99.86495) (xy 218.901974 100.557767) (xy 219.432233 101.088026) (xy 220.12505 101.375)
(xy 220.87495 101.375) (xy 221.284741 101.205259) (xy 221.115 101.61505) (xy 221.115 102.36495) (xy 221.284741 102.774741)
(xy 220.87495 102.605) (xy 220.12505 102.605) (xy 219.432233 102.891974) (xy 218.901974 103.422233) (xy 218.615 104.11505)
(xy 218.615 104.86495) (xy 218.901974 105.557767) (xy 219.432233 106.088026) (xy 220.12505 106.375) (xy 220.87495 106.375)
(xy 221.284741 106.205259) (xy 221.115 106.61505) (xy 221.115 107.36495) (xy 221.284741 107.774741) (xy 220.87495 107.605)
(xy 220.12505 107.605) (xy 219.432233 107.891974) (xy 218.901974 108.422233) (xy 218.615 109.11505) (xy 218.615 109.86495)
(xy 218.901974 110.557767) (xy 219.432233 111.088026) (xy 220.12505 111.375) (xy 220.87495 111.375) (xy 221.284741 111.205259)
(xy 221.115 111.61505) (xy 221.115 112.36495) (xy 221.284741 112.774741) (xy 220.87495 112.605) (xy 220.12505 112.605)
(xy 219.432233 112.891974) (xy 218.901974 113.422233) (xy 218.615 114.11505) (xy 218.615 114.86495) (xy 218.901974 115.557767)
(xy 219.432233 116.088026) (xy 220.12505 116.375) (xy 220.87495 116.375) (xy 221.284741 116.205259) (xy 221.115 116.61505)
(xy 221.115 116.713) (xy 210.82 116.713) (xy 210.771399 116.722667) (xy 210.730197 116.750197) (xy 195.527394 131.953)
(xy 138.557 131.953) (xy 138.557 129.604523) (xy 138.652235 129.668157) (xy 138.9 129.71744) (xy 140.5 129.71744)
(xy 140.747765 129.668157) (xy 140.957809 129.527809) (xy 141.098157 129.317765) (xy 141.145451 129.08) (xy 154.71256 129.08)
(xy 154.71256 129.12) (xy 154.761843 129.367765) (xy 154.902191 129.577809) (xy 155.112235 129.718157) (xy 155.36 129.76744)
(xy 157.06 129.76744) (xy 157.307765 129.718157) (xy 157.517809 129.577809) (xy 157.658157 129.367765) (xy 157.70744 129.12)
(xy 157.70744 129.08) (xy 159.940227 129.08) (xy 160.02 129.095868) (xy 160.099773 129.08) (xy 160.099774 129.08)
(xy 160.336046 129.033003) (xy 160.603977 128.853977) (xy 160.649168 128.786344) (xy 162.441347 126.994166) (xy 162.508977 126.948977)
(xy 162.688003 126.681046) (xy 162.735 126.444774) (xy 162.735 126.444773) (xy 162.750868 126.365) (xy 162.735 126.285227)
(xy 162.735 118.445512) (xy 163.530513 117.65) (xy 177.085227 117.65) (xy 177.165 117.665868) (xy 177.244773 117.65)
(xy 177.244774 117.65) (xy 177.481046 117.603003) (xy 177.748977 117.423977) (xy 177.794168 117.356344) (xy 178.951348 116.199165)
(xy 179.018977 116.153977) (xy 179.198003 115.886046) (xy 179.245 115.649774) (xy 179.245 115.649773) (xy 179.260868 115.570001)
(xy 179.245 115.490226) (xy 179.245 100.295614) (xy 179.405 100.32744) (xy 180.005 100.32744) (xy 180.252765 100.278157)
(xy 180.34 100.219868) (xy 180.427235 100.278157) (xy 180.675 100.32744) (xy 181.275 100.32744) (xy 181.522765 100.278157)
(xy 181.61 100.219868) (xy 181.697235 100.278157) (xy 181.945 100.32744) (xy 182.545 100.32744) (xy 182.792765 100.278157)
(xy 182.88 100.219868) (xy 182.967235 100.278157) (xy 183.215 100.32744) (xy 183.815 100.32744) (xy 183.900001 100.310533)
(xy 183.900001 100.665285) (xy 183.801261 100.731261) (xy 183.613495 101.012273) (xy 183.54756 101.34375) (xy 183.54756 101.85625)
(xy 183.613495 102.187727) (xy 183.801261 102.468739) (xy 184.082273 102.656505) (xy 184.41375 102.72244) (xy 184.85125 102.72244)
(xy 185.182727 102.656505) (xy 185.345031 102.548057) (xy 185.410302 102.613327) (xy 185.643691 102.71) (xy 185.92175 102.71)
(xy 186.0805 102.55125) (xy 186.0805 101.727) (xy 186.3345 101.727) (xy 186.3345 102.55125) (xy 186.49325 102.71)
(xy 186.771309 102.71) (xy 187.004698 102.613327) (xy 187.183327 102.434699) (xy 187.28 102.20131) (xy 187.28 101.88575)
(xy 187.12125 101.727) (xy 186.3345 101.727) (xy 186.0805 101.727) (xy 186.0605 101.727) (xy 186.0605 101.473)
(xy 186.0805 101.473) (xy 186.0805 100.64875) (xy 186.3345 100.64875) (xy 186.3345 101.473) (xy 187.12125 101.473)
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add ground and power planes
2018-08-28 21:14:49 +00:00
)
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)
start pcb layout
2018-08-26 19:54:32 +00:00
)