100 lines
3.3 KiB
C
100 lines
3.3 KiB
C
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/*
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* File: rateLimiter.h
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*
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* Code generated for Simulink model 'rateLimiter'.
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*
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* Model version : 1.1186
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* Simulink Coder version : 8.13 (R2017b) 24-Jul-2017
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* C/C++ source code generated on : Sun Oct 27 16:29:07 2019
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*
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* Target selection: ert.tlc
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* Embedded hardware selection: ARM Compatible->ARM Cortex
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* Emulation hardware selection:
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* Differs from embedded hardware (MATLAB Host)
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* Code generation objectives:
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* 1. Execution efficiency
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* 2. RAM efficiency
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* Validation result: Not run
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*/
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#ifndef RTW_HEADER_rateLimiter_h_
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#define RTW_HEADER_rateLimiter_h_
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#ifndef rateLimiter_COMMON_INCLUDES_
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# define rateLimiter_COMMON_INCLUDES_
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#include "rtwtypes.h"
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#endif /* rateLimiter_COMMON_INCLUDES_ */
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/* Macros for accessing real-time model data structure */
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/* Forward declaration for rtModel */
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typedef struct tag_RTM RT_MODEL;
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/* Block signals and states (auto storage) for system '<Root>/rateLimiter' */
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typedef struct {
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int16_T UnitDelay_DSTATE; /* '<S2>/UnitDelay' */
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} DW_rateLimiter;
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/* Block signals and states (auto storage) for system '<Root>' */
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typedef struct {
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DW_rateLimiter rateLimiter_j0; /* '<Root>/rateLimiter' */
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} DW;
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/* External inputs (root inport signals with auto storage) */
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typedef struct {
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int16_T u; /* '<Root>/u' */
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int16_T rate; /* '<Root>/rate' */
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} ExtU;
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/* External outputs (root outports fed by signals with auto storage) */
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typedef struct {
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int16_T y; /* '<Root>/y' */
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} ExtY;
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/* Real-time Model Data Structure */
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struct tag_RTM {
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ExtU *inputs;
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ExtY *outputs;
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DW *dwork;
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};
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/* Model entry point functions */
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extern void rateLimiter_initialize(RT_MODEL *const rtM);
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extern void rateLimiter_step(RT_MODEL *const rtM);
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/*-
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* These blocks were eliminated from the model due to optimizations:
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*
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* Block '<S3>/Data Type Duplicate' : Unused code path elimination
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* Block '<S3>/Data Type Propagation' : Unused code path elimination
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*/
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/*-
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* The generated code includes comments that allow you to trace directly
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* back to the appropriate location in the model. The basic format
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* is <system>/block_name, where system is the system number (uniquely
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* assigned by Simulink) and block_name is the name of the block.
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*
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* Note that this particular code originates from a subsystem build,
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* and has its own system numbers different from the parent model.
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* Refer to the system hierarchy for this subsystem below, and use the
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* MATLAB hilite_system command to trace the generated code back
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* to the parent model. For example,
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*
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* hilite_system('BLDCmotorControl_FOC_R2017b_fixdt/rateLimiter') - opens subsystem BLDCmotorControl_FOC_R2017b_fixdt/rateLimiter
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* hilite_system('BLDCmotorControl_FOC_R2017b_fixdt/rateLimiter/Kp') - opens and selects block Kp
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*
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* Here is the system hierarchy for this model
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*
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* '<Root>' : 'BLDCmotorControl_FOC_R2017b_fixdt'
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* '<S1>' : 'BLDCmotorControl_FOC_R2017b_fixdt/rateLimiter'
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* '<S2>' : 'BLDCmotorControl_FOC_R2017b_fixdt/rateLimiter/Rate_Limiter'
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* '<S3>' : 'BLDCmotorControl_FOC_R2017b_fixdt/rateLimiter/Rate_Limiter/Saturation Dynamic'
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*/
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#endif /* RTW_HEADER_rateLimiter_h_ */
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/*
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* File trailer for generated code.
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*
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* [EOF]
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*/
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