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audiomixer/schematic/baseplate_in_output/baseplate_in_output.kicad_pcb

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change pcie pinout
2019-04-14 18:01:42 +00:00
(kicad_pcb (version 20171130) (host pcbnew 5.0.2-bee76a0~70~ubuntu16.04.1)
(general
(thickness 1.6)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(drawings 16)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(tracks 152)
change pcie pinout
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(zones 0)
add baseplate edgesolderstrips
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(modules 17)
change pcie pinout
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(nets 10)
)
(page A4)
(layers
(0 F.Cu signal)
(31 B.Cu signal)
(32 B.Adhes user)
(33 F.Adhes user)
(34 B.Paste user)
(35 F.Paste user)
(36 B.SilkS user)
(37 F.SilkS user)
(38 B.Mask user)
(39 F.Mask user)
(40 Dwgs.User user)
(41 Cmts.User user)
(42 Eco1.User user)
(43 Eco2.User user)
(44 Edge.Cuts user)
(45 Margin user)
(46 B.CrtYd user)
(47 F.CrtYd user)
(48 B.Fab user)
(49 F.Fab user)
)
(setup
(last_trace_width 1)
(trace_clearance 0.2)
add baseplate edgesolderstrips
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(zone_clearance 0.5)
change pcie pinout
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(zone_45_only no)
(trace_min 0.2)
(segment_width 0.2)
(edge_width 0.1)
(via_size 0.8)
(via_drill 0.4)
(via_min_size 0.4)
(via_min_drill 0.3)
(uvia_size 0.3)
(uvia_drill 0.1)
(uvias_allowed no)
(uvia_min_size 0.2)
(uvia_min_drill 0.1)
(pcb_text_width 0.3)
(pcb_text_size 1.5 1.5)
(mod_edge_width 0.15)
(mod_text_size 1 1)
(mod_text_width 0.15)
(pad_size 6.4 6.4)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(pad_drill 3.1)
change pcie pinout
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(pad_to_mask_clearance 0)
(solder_mask_min_width 0.25)
(aux_axis_origin 0 0)
(visible_elements FFFFFF7F)
(pcbplotparams
widen silkscreen on pcie connector footprint
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(layerselection 0x010f0_ffffffff)
change pcie pinout
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(usegerberextensions false)
change settings for gerber plot
2019-06-19 08:25:20 +00:00
(usegerberattributes true)
change pcie pinout
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(usegerberadvancedattributes false)
(creategerberjobfile false)
widen silkscreen on pcie connector footprint
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(excludeedgelayer false)
change pcie pinout
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(linewidth 0.100000)
(plotframeref false)
(viasonmask false)
(mode 1)
(useauxorigin false)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(psnegative false)
(psa4output false)
(plotreference true)
(plotvalue true)
(plotinvisibletext false)
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(padsonsilk true)
change pcie pinout
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(subtractmaskfromsilk false)
(outputformat 1)
(mirror false)
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(drillshape 0)
change pcie pinout
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(scaleselection 1)
widen silkscreen on pcie connector footprint
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(outputdirectory "plots/"))
change pcie pinout
2019-04-14 18:01:42 +00:00
)
(net 0 "")
(net 1 GNDA)
(net 2 inA-)
(net 3 inA+)
(net 4 inB+)
(net 5 inB-)
(net 6 outB)
(net 7 outA)
(net 8 +15V)
(net 9 -15V)
(net_class Default "This is the default net class."
(clearance 0.2)
(trace_width 1)
(via_dia 0.8)
(via_drill 0.4)
(uvia_dia 0.3)
(uvia_drill 0.1)
(add_net +15V)
(add_net -15V)
(add_net GNDA)
(add_net inA+)
(add_net inA-)
(add_net inB+)
(add_net inB-)
(add_net outA)
(add_net outB)
)
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(module footprints:PCIexpress_1x_connector (layer F.Cu) (tedit 5D08AB2A) (tstamp 5CB1E174)
change pcie pinout
2019-04-14 18:01:42 +00:00
(at 38.1 45.72 90)
(path /5CB5100B)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(fp_text reference J1 (at -2 2.54 90) (layer F.SilkS) hide
change pcie pinout
2019-04-14 18:01:42 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_02x18_Row_Letter_Last (at 5.08 -3.81 90) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(fp_line (start -3 -2.8) (end 22 -2.8) (layer F.SilkS) (width 0.15))
(fp_line (start 22 -2.8) (end 22 5) (layer F.SilkS) (width 0.15))
(fp_line (start 22 5.3) (end -3 5.3) (layer F.SilkS) (width 0.15))
(fp_line (start -3 5) (end -3 -2.8) (layer F.SilkS) (width 0.15))
change pcie pinout
2019-04-14 18:01:42 +00:00
(fp_line (start 22 5) (end 22 5.5) (layer F.SilkS) (width 0.15))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(fp_line (start 22 5.5) (end -3 5.5) (layer F.SilkS) (width 0.15))
(fp_line (start -3 5.5) (end -3 5) (layer F.SilkS) (width 0.15))
(pad 1a thru_hole rect (at 0 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 9 -15V))
(pad 2a thru_hole circle (at 1 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 9 -15V))
(pad 3a thru_hole circle (at 2 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 9 -15V))
(pad 4a thru_hole circle (at 3 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 5a thru_hole circle (at 4 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 6a thru_hole circle (at 5 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 7a thru_hole circle (at 6 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 8 +15V))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 8a thru_hole circle (at 7 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 8 +15V))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 9a thru_hole circle (at 8 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 8 +15V))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 10a thru_hole circle (at 9 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 11a thru_hole circle (at 10 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 12a thru_hole circle (at 13 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 2 inA-))
(pad 13a thru_hole circle (at 14 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 14a thru_hole circle (at 15 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 3 inA+))
(pad 15a thru_hole circle (at 16 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
(pad 16a thru_hole circle (at 17 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 5 inB-))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 17a thru_hole circle (at 18 0 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 18a thru_hole circle (at 19 -2 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 4 inB+))
(pad 1b thru_hole circle (at 0 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 9 -15V))
(pad 2b thru_hole circle (at 1 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 9 -15V))
(pad 3b thru_hole circle (at 2 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 9 -15V))
(pad 4b thru_hole circle (at 3 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 5b thru_hole circle (at 4 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 6b thru_hole circle (at 5 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 7b thru_hole circle (at 6 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 8 +15V))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 8b thru_hole circle (at 7 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 8 +15V))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 9b thru_hole circle (at 8 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 8 +15V))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 10b thru_hole circle (at 9 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 11b thru_hole circle (at 10 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 12b thru_hole circle (at 13 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
change pcie pinout
2019-04-14 18:01:42 +00:00
(net 1 GNDA))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(pad 13b thru_hole circle (at 14 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 7 outA))
(pad 14b thru_hole circle (at 15 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 7 outA))
(pad 15b thru_hole circle (at 16 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 1 GNDA))
(pad 16b thru_hole circle (at 17 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 6 outB))
(pad 17b thru_hole circle (at 18 2.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 6 outB))
(pad 18b thru_hole circle (at 19 4.5 90) (size 1.2 1.2) (drill 0.7) (layers *.Cu *.Mask)
(net 1 GNDA))
(pad "" thru_hole circle (at 11.65 1.25 90) (size 2.35 2.35) (drill 2.35) (layers *.Cu *.Mask))
(pad "" thru_hole circle (at 20.65 1.25 90) (size 2.35 2.35) (drill 2.35) (layers *.Cu *.Mask))
change pcie pinout
2019-04-14 18:01:42 +00:00
)
(module footprints:coax_solder_pad (layer F.Cu) (tedit 5CB36FFB) (tstamp 5CB1E198)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(at 49.53 26.67 270)
change pcie pinout
2019-04-14 18:01:42 +00:00
(path /5CB301F1)
(fp_text reference outA1 (at 5.715 -2.54 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x02 (at 3.81 -3.81 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.54 1.27) (end -2.54 -2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 1.27) (end -2.54 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 -1.27) (end 7.62 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 -1.27) (end 7.62 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 2.54 -2.54) (end 5.08 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -2.54 -2.54) (end 2.54 -2.54) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole roundrect (at 5.08 0 270) (size 4 2) (drill 0.8 (offset 0.254 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 7 outA))
(pad 1 thru_hole roundrect (at 0 0 270) (size 4 3) (drill 0.8 (offset -0.254 -0.635)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 1 GNDA))
)
(module footprints:coax_solder_pad (layer F.Cu) (tedit 5CB36FFF) (tstamp 5CB1E1B0)
(at 45.72 20.32 270)
(path /5CB3167B)
(fp_text reference outB1 (at 1.27 1.905 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x02 (at 3.81 -3.81 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.54 -2.54) (end 2.54 -2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 2.54 -2.54) (end 5.08 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 -1.27) (end 7.62 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 -1.27) (end 7.62 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 1.27) (end -2.54 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -2.54 1.27) (end -2.54 -2.54) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole roundrect (at 0 0 270) (size 4 3) (drill 0.8 (offset -0.254 -0.635)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 1 GNDA))
(pad 2 thru_hole roundrect (at 5.08 0 270) (size 4 2) (drill 0.8 (offset 0.254 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 6 outB))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(module MountingHole:MountingHole_3.2mm_M3_Pad (layer F.Cu) (tedit 5CE3BF4A) (tstamp 5CBFFFEE)
change pcie pinout
2019-04-14 18:01:42 +00:00
(at 39.37 18.415)
(descr "Mounting Hole 3.2mm, M3")
(tags "mounting hole 3.2mm m3")
(attr virtual)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide
change pcie pinout
2019-04-14 18:01:42 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MountingHole_3.2mm_M3_Pad (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(pad 1 thru_hole circle (at 0 0) (size 6.4 6.4) (drill 3.1) (layers *.Cu *.Mask))
change pcie pinout
2019-04-14 18:01:42 +00:00
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(module MountingHole:MountingHole_3.2mm_M3_Pad (layer F.Cu) (tedit 5CE3BF4F) (tstamp 5CBFFFFE)
change pcie pinout
2019-04-14 18:01:42 +00:00
(at 39.37 53.34)
(descr "Mounting Hole 3.2mm, M3")
(tags "mounting hole 3.2mm m3")
(attr virtual)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(fp_text reference REF** (at 0 -4.2) (layer F.SilkS) hide
change pcie pinout
2019-04-14 18:01:42 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value MountingHole_3.2mm_M3_Pad (at 0 4.2) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_circle (center 0 0) (end 3.45 0) (layer F.CrtYd) (width 0.05))
(fp_circle (center 0 0) (end 3.2 0) (layer Cmts.User) (width 0.15))
(fp_text user %R (at 0.3 0) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(pad 1 thru_hole circle (at 0 0.075) (size 6.4 6.4) (drill 3.1) (layers *.Cu *.Mask))
change pcie pinout
2019-04-14 18:01:42 +00:00
)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(module footprints:coax_solder_pad_flipped (layer F.Cu) (tedit 5CD00F94) (tstamp 5CD0104B)
(at 29.21 26.67 270)
(path /5CB2B45C)
(fp_text reference inA1 (at 3.57 -1.785 270) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value Conn_01x02 (at 3.57 -3.57 270) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_line (start -2.54 -1.27) (end -2.54 2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 1.27) (end 7.62 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 1.27) (end 7.62 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 2.54 2.54) (end 5.08 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -2.54 2.54) (end 2.54 2.54) (layer F.SilkS) (width 0.15))
(pad 2 thru_hole roundrect (at 5.08 0 90) (size 4 2) (drill 0.8 (offset -0.254 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 2 inA-))
(pad 1 thru_hole roundrect (at 0 0 90) (size 4 3) (drill 0.8 (offset 0.254 -0.635)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 3 inA+))
)
(module footprints:coax_solder_pad_flipped (layer F.Cu) (tedit 5CD00FB3) (tstamp 5CD00EB3)
(at 33.02 20.32 270)
(path /5CB2D8FB)
(fp_text reference inB1 (at 3.57 -1.785 270) (layer F.SilkS) hide
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)
(fp_text value Conn_01x02 (at 3.57 -3.57 270) (layer F.Fab)
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)
(fp_line (start -2.54 2.54) (end 2.54 2.54) (layer F.SilkS) (width 0.15))
(fp_line (start 2.54 2.54) (end 5.08 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 5.08 1.27) (end 7.62 1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 1.27) (end 7.62 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start 7.62 -1.27) (end -2.54 -1.27) (layer F.SilkS) (width 0.15))
(fp_line (start -2.54 -1.27) (end -2.54 2.54) (layer F.SilkS) (width 0.15))
(pad 1 thru_hole roundrect (at 0 0 90) (size 4 3) (drill 0.8 (offset 0.254 -0.635)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 4 inB+))
(pad 2 thru_hole roundrect (at 5.08 0 90) (size 4 2) (drill 0.8 (offset -0.254 0)) (layers *.Cu *.Mask) (roundrect_rratio 0.25)
(net 5 inB-))
)
(module footprints:edge_solderstrip_1mm5x6mm (layer F.Cu) (tedit 5CD017A5) (tstamp 5CD01BF3)
(at 49.53 45.085)
(path /5CD03267)
(fp_text reference J2 (at 11.43 0) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value -15V (at 0 -1.785) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd roundrect (at 0 0) (size 6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.1)
(net 9 -15V))
)
(module footprints:edge_solderstrip_1mm5x6mm (layer F.Cu) (tedit 5CD01851) (tstamp 5CD01B16)
(at 29.21 41.91 180)
(path /5CD03404)
(fp_text reference J3 (at 5.355 0 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GND (at 0 -1.785 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd roundrect (at 0 0 180) (size 6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.1)
(net 1 GNDA))
)
(module footprints:edge_solderstrip_1mm5x6mm (layer F.Cu) (tedit 5CD0184D) (tstamp 5CD01B1B)
(at 29.21 38.735 180)
(path /5CD03422)
(fp_text reference J4 (at 5.355 0 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value +15V (at 0 -1.785 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd roundrect (at 0 0 180) (size 6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.1)
(net 8 +15V))
)
(module footprints:edge_solderstrip_1mm5x6mm (layer F.Cu) (tedit 5CD01854) (tstamp 5CD01B20)
(at 29.21 45.085 180)
(path /5CD08F50)
(fp_text reference J5 (at 5.355 0 180) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value -15V (at 0 -1.785 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd roundrect (at 0 0 180) (size 6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.1)
(net 9 -15V))
)
(module footprints:edge_solderstrip_1mm5x6mm (layer F.Cu) (tedit 5CD01848) (tstamp 5CD01BBA)
(at 49.53 41.91)
(path /5CD08F56)
(fp_text reference J6 (at 5.355 0) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GND (at 0 -1.785) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd roundrect (at 0 0) (size 6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.1)
(net 1 GNDA))
)
(module footprints:edge_solderstrip_1mm5x6mm (layer F.Cu) (tedit 5CD0184B) (tstamp 5CD01B2A)
(at 49.53 38.735)
(path /5CD08F5C)
(fp_text reference J7 (at 5.355 0) (layer F.SilkS) hide
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value +15V (at 0 -1.785) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 smd roundrect (at 0 0) (size 6 1.5) (layers F.Cu F.Paste F.Mask) (roundrect_rratio 0.1)
(net 8 +15V))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(module footprints:edge_solderstrip_th (layer F.Cu) (tedit 5CE3BEE1) (tstamp 5CD01FF0)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(at 49.53 14.605)
(path /5CD13694)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(fp_text reference J8 (at 5.355 0) (layer F.SilkS) hide
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GND (at 0 -1.785) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole roundrect (at 0 0) (size 6 1.5) (drill 0.8) (layers *.Cu *.Mask) (roundrect_rratio 0.1)
(net 1 GNDA))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(module footprints:edge_solderstrip_th (layer F.Cu) (tedit 5CE3BEDE) (tstamp 5CE3C4F9)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(at 29.21 14.605 180)
(path /5CD1356B)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(fp_text reference J9 (at 5.355 0 180) (layer F.SilkS) hide
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GND (at 0 -1.785 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole roundrect (at 0 0 180) (size 6 1.5) (drill 0.8) (layers *.Cu *.Mask) (roundrect_rratio 0.1)
(net 1 GNDA))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(module footprints:edge_solderstrip_th (layer F.Cu) (tedit 5CE3BEE5) (tstamp 5CD01FF8)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(at 49.53 56.515)
(path /5CD1363E)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(fp_text reference J10 (at 5.355 0) (layer F.SilkS) hide
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GND (at 0 -1.785) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole roundrect (at 0 0) (size 6 1.5) (drill 0.8) (layers *.Cu *.Mask) (roundrect_rratio 0.1)
(net 1 GNDA))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(module footprints:edge_solderstrip_th (layer F.Cu) (tedit 5CE3BEE9) (tstamp 5CD01FFC)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(at 29.21 56.515 180)
(path /5CD13668)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(fp_text reference J11 (at 5.355 0 180) (layer F.SilkS) hide
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(effects (font (size 1 1) (thickness 0.15)))
)
(fp_text value GND (at 0 -1.785 180) (layer F.Fab)
(effects (font (size 1 1) (thickness 0.15)))
)
(pad 1 thru_hole roundrect (at 0 0 180) (size 6 1.5) (drill 0.8) (layers *.Cu *.Mask) (roundrect_rratio 0.1)
(net 1 GNDA))
)
(gr_text - (at 33.02 45.085) (layer F.SilkS) (tstamp 5CD01D97)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text + (at 33.02 38.735) (layer F.SilkS) (tstamp 5CD01D96)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text GND (at 33.655 41.91) (layer F.SilkS) (tstamp 5CD01D92)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text - (at 45.72 45.085) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text GND (at 45.085 41.91) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text + (at 45.72 38.735) (layer F.SilkS)
(effects (font (size 1 1) (thickness 0.2)))
)
(gr_text B (at 28.575 20.32) (layer F.SilkS) (tstamp 5CD01003)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
)
(gr_text A (at 46.355 29.845) (layer F.SilkS) (tstamp 5CD01003)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
)
change pcie pinout
2019-04-14 18:01:42 +00:00
(gr_line (start 25.4 58.42) (end 25.4 12.7) (layer Edge.Cuts) (width 0.1))
(gr_line (start 53.34 58.42) (end 25.4 58.42) (layer Edge.Cuts) (width 0.1))
(gr_line (start 53.34 12.7) (end 53.34 58.42) (layer Edge.Cuts) (width 0.1))
(gr_line (start 25.4 12.7) (end 53.34 12.7) (layer Edge.Cuts) (width 0.1))
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(gr_text A (at 30.48 29.845) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
change pcie pinout
2019-04-14 18:01:42 +00:00
)
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(gr_text B (at 48.26 20.32) (layer F.SilkS)
(effects (font (size 1.5 1.5) (thickness 0.3)) (justify left))
change pcie pinout
2019-04-14 18:01:42 +00:00
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(gr_text In (at 32.385 33.655) (layer F.SilkS)
change pcie pinout
2019-04-14 18:01:42 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(gr_text Out (at 45.72 33.655) (layer F.SilkS)
change pcie pinout
2019-04-14 18:01:42 +00:00
(effects (font (size 1.5 1.5) (thickness 0.3)))
)
(segment (start 40.6 29.72) (end 38.1 29.72) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 29.72) (end 38.1 27.72) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 31.72) (end 38.1 29.72) (width 1) (layer B.Cu) (net 1))
(segment (start 42.6 33.72) (end 42.6 32.72) (width 1) (layer B.Cu) (net 1))
(segment (start 40.6 35.72) (end 42.6 33.72) (width 1) (layer B.Cu) (net 1))
(segment (start 41.6 35.72) (end 42.6 36.72) (width 1) (layer B.Cu) (net 1))
(segment (start 40.6 35.72) (end 41.6 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 37.1 35.72) (end 36.1 36.72) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 35.72) (end 37.1 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 39.875003 36.319999) (end 38.699999 36.319999) (width 1) (layer B.Cu) (net 1))
(segment (start 40.475002 35.72) (end 39.875003 36.319999) (width 1) (layer B.Cu) (net 1))
(segment (start 38.699999 36.319999) (end 38.1 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 40.6 35.72) (end 40.475002 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 41.6 41.72) (end 42.6 40.72) (width 1) (layer B.Cu) (net 1))
(segment (start 40.6 41.72) (end 41.6 41.72) (width 1) (layer B.Cu) (net 1))
(segment (start 42.6 42.72) (end 41.6 41.72) (width 1) (layer B.Cu) (net 1))
(segment (start 37.1 41.72) (end 36.1 40.72) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 41.72) (end 37.1 41.72) (width 1) (layer B.Cu) (net 1))
(segment (start 36.1 42.72) (end 37.1 41.72) (width 1) (layer B.Cu) (net 1))
(segment (start 37.474999 32.345001) (end 37.500001 32.319999) (width 1) (layer B.Cu) (net 1))
(segment (start 37.500001 32.319999) (end 38.1 31.72) (width 1) (layer B.Cu) (net 1))
(segment (start 37.474999 35.094999) (end 37.474999 32.345001) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 35.72) (end 37.474999 35.094999) (width 1) (layer B.Cu) (net 1))
(segment (start 37.474999 23.485001) (end 38.1 22.86) (width 1) (layer B.Cu) (net 1))
(segment (start 42.6 26.72) (end 42.6 22.86) (width 1) (layer B.Cu) (net 1))
(segment (start 37.474999 27.094999) (end 37.474999 23.485001) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 27.72) (end 37.474999 27.094999) (width 1) (layer B.Cu) (net 1))
(segment (start 42.6 22.17) (end 42.6 22.86) (width 1) (layer B.Cu) (net 1))
(segment (start 44.45 20.32) (end 42.6 22.17) (width 1) (layer B.Cu) (net 1))
(segment (start 45.72 20.32) (end 44.45 20.32) (width 1) (layer B.Cu) (net 1))
(segment (start 39.37 22.86) (end 42.6 22.86) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 22.86) (end 39.37 22.86) (width 1) (layer B.Cu) (net 1))
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(segment (start 49.53 26.67) (end 49.53 21.59) (width 1) (layer B.Cu) (net 1))
(segment (start 49.53 21.59) (end 48.26 20.32) (width 1) (layer B.Cu) (net 1))
(segment (start 48.26 20.32) (end 45.72 20.32) (width 1) (layer B.Cu) (net 1))
(segment (start 42.6 36.72) (end 43.199999 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 43.199999 36.120001) (end 43.224001 36.144003) (width 1) (layer B.Cu) (net 1))
(segment (start 42.799998 35.72) (end 43.224001 36.144003) (width 1) (layer B.Cu) (net 1))
(segment (start 40.6 35.72) (end 42.799998 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 35.900002 35.72) (end 35.500001 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 38.1 35.72) (end 35.900002 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 42.6 40.72) (end 42.6 42.72) (width 1) (layer F.Cu) (net 1))
(segment (start 36.1 40.72) (end 36.1 42.72) (width 1) (layer F.Cu) (net 1))
(segment (start 37.1 41.72) (end 36.1 40.72) (width 1) (layer F.Cu) (net 1))
(segment (start 37.1 41.72) (end 36.1 42.72) (width 1) (layer F.Cu) (net 1))
(segment (start 38.1 41.72) (end 37.1 41.72) (width 1) (layer F.Cu) (net 1))
(segment (start 41.6 41.72) (end 42.6 40.72) (width 1) (layer F.Cu) (net 1))
(segment (start 41.6 41.72) (end 42.6 42.72) (width 1) (layer F.Cu) (net 1))
(segment (start 40.6 41.72) (end 41.6 41.72) (width 1) (layer F.Cu) (net 1))
(segment (start 36.1 40.72) (end 33.735 40.72) (width 1) (layer B.Cu) (net 1))
(segment (start 33.735 40.72) (end 33.02 40.005) (width 1) (layer B.Cu) (net 1))
(segment (start 33.02 40.005) (end 33.02 37.465) (width 1) (layer B.Cu) (net 1))
(segment (start 35.500001 36.120001) (end 34.364999 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 36.1 36.72) (end 35.500001 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 36.1 42.72) (end 33.48 42.72) (width 1) (layer B.Cu) (net 1))
(segment (start 33.48 42.72) (end 33.48 47.525) (width 1) (layer B.Cu) (net 1))
(segment (start 40.79 41.91) (end 40.6 41.72) (width 1) (layer F.Cu) (net 1))
(segment (start 50.165 41.91) (end 40.79 41.91) (width 1) (layer F.Cu) (net 1))
(segment (start 37.91 41.91) (end 38.1 41.72) (width 1) (layer F.Cu) (net 1))
(segment (start 28.575 41.91) (end 37.91 41.91) (width 1) (layer F.Cu) (net 1))
disconnect screws from agnd
2019-05-21 09:07:08 +00:00
(segment (start 43.18 14.605) (end 49.53 14.605) (width 1) (layer B.Cu) (net 1))
(segment (start 29.21 14.605) (end 36.195 14.605) (width 1) (layer B.Cu) (net 1))
(segment (start 42.545 13.97) (end 43.18 14.605) (width 1) (layer B.Cu) (net 1))
(segment (start 36.195 14.605) (end 36.83 13.97) (width 1) (layer B.Cu) (net 1))
(segment (start 36.83 13.97) (end 42.545 13.97) (width 1) (layer B.Cu) (net 1))
(segment (start 29.21 51.795) (end 33.48 47.525) (width 1) (layer B.Cu) (net 1))
(segment (start 29.21 56.515) (end 29.21 51.795) (width 1) (layer B.Cu) (net 1))
(segment (start 44.45 48.26) (end 34.215 48.26) (width 1) (layer B.Cu) (net 1))
(segment (start 49.53 53.34) (end 44.45 48.26) (width 1) (layer B.Cu) (net 1))
(segment (start 34.215 48.26) (end 33.48 47.525) (width 1) (layer B.Cu) (net 1))
(segment (start 49.53 56.515) (end 49.53 53.34) (width 1) (layer B.Cu) (net 1))
(segment (start 26.67 17.145) (end 29.21 14.605) (width 1) (layer B.Cu) (net 1))
(segment (start 27.230001 36.120001) (end 26.37499 35.26499) (width 1) (layer B.Cu) (net 1))
(segment (start 26.37499 17.44001) (end 26.67 17.145) (width 1) (layer B.Cu) (net 1))
(segment (start 33.02 37.465) (end 33.02 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 33.02 36.120001) (end 27.230001 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 34.364999 36.120001) (end 33.02 36.120001) (width 1) (layer B.Cu) (net 1))
(segment (start 52.07 34.29) (end 50.64 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 50.64 35.72) (end 42.799998 35.72) (width 1) (layer B.Cu) (net 1))
(segment (start 49.53 14.605) (end 52.07 17.145) (width 1) (layer B.Cu) (net 1))
(segment (start 52.705 33.655) (end 52.07 34.29) (width 0.5) (layer B.Cu) (net 1))
(segment (start 52.07 17.145) (end 52.705 17.78) (width 0.5) (layer B.Cu) (net 1))
(segment (start 26.37499 35.26499) (end 26.37499 17.44001) (width 0.5) (layer B.Cu) (net 1))
(segment (start 52.705 17.78) (end 52.705 33.655) (width 0.5) (layer B.Cu) (net 1))
(segment (start 52.07 29.21) (end 52.07 34.29) (width 1) (layer B.Cu) (net 1))
(segment (start 49.53 26.67) (end 52.07 29.21) (width 1) (layer B.Cu) (net 1))
widen silkscreen on pcie connector footprint
2019-06-18 09:54:05 +00:00
(segment (start 38.1 41.72) (end 40.6 41.72) (width 1) (layer B.Cu) (net 1))
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(segment (start 30.18 32.72) (end 36.1 32.72) (width 1) (layer B.Cu) (net 2))
(segment (start 29.21 31.75) (end 30.18 32.72) (width 1) (layer B.Cu) (net 2))
(segment (start 36.1 30.72) (end 33.26 30.72) (width 1) (layer B.Cu) (net 3))
(segment (start 33.26 30.72) (end 29.21 26.67) (width 1) (layer B.Cu) (net 3))
change pcie pinout
2019-04-14 18:01:42 +00:00
(segment (start 36.1 22.13) (end 34.29 20.32) (width 1) (layer B.Cu) (net 4))
(segment (start 36.1 26.72) (end 36.1 22.13) (width 1) (layer B.Cu) (net 4))
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(segment (start 33.02 20.32) (end 34.29 20.32) (width 1) (layer B.Cu) (net 4))
change pcie pinout
2019-04-14 18:01:42 +00:00
(segment (start 36.1 28.72) (end 33.8 28.72) (width 1) (layer B.Cu) (net 5))
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(segment (start 33.02 27.94) (end 33.02 25.4) (width 1) (layer B.Cu) (net 5))
(segment (start 33.8 28.72) (end 33.02 27.94) (width 1) (layer B.Cu) (net 5))
change pcie pinout
2019-04-14 18:01:42 +00:00
(segment (start 45.72 25.524002) (end 45.72 25.4) (width 1) (layer B.Cu) (net 6))
(segment (start 45.72 27.94) (end 45.72 25.524002) (width 1) (layer B.Cu) (net 6))
(segment (start 44.94 28.72) (end 45.72 27.94) (width 1) (layer B.Cu) (net 6))
(segment (start 42.6 28.72) (end 44.94 28.72) (width 1) (layer B.Cu) (net 6))
(segment (start 42.055 28.72) (end 42.6 28.72) (width 1) (layer B.Cu) (net 6))
(segment (start 41.055 27.72) (end 42.055 28.72) (width 1) (layer B.Cu) (net 6))
(segment (start 40.6 27.72) (end 41.055 27.72) (width 1) (layer B.Cu) (net 6))
(segment (start 41.245 31.72) (end 40.6 31.72) (width 1) (layer B.Cu) (net 7))
(segment (start 42.245 30.72) (end 41.245 31.72) (width 1) (layer B.Cu) (net 7))
(segment (start 42.6 30.72) (end 42.245 30.72) (width 1) (layer B.Cu) (net 7))
add baseplate edgesolderstrips
2019-05-06 11:31:55 +00:00
(segment (start 49.53 31.75) (end 46.99 31.75) (width 1) (layer B.Cu) (net 7))
(segment (start 45.96 30.72) (end 42.6 30.72) (width 1) (layer B.Cu) (net 7))
(segment (start 46.99 31.75) (end 45.96 30.72) (width 1) (layer B.Cu) (net 7))
change pcie pinout
2019-04-14 18:01:42 +00:00
(segment (start 41.6 38.72) (end 40.6 39.72) (width 1) (layer B.Cu) (net 8))
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2019-05-06 11:31:55 +00:00
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2019-06-18 09:54:05 +00:00
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2019-04-14 18:01:42 +00:00
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2019-05-06 11:31:55 +00:00
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2019-06-18 09:54:05 +00:00
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2019-04-14 18:01:42 +00:00
change settings for gerber plot
2019-06-19 08:25:20 +00:00
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2019-05-06 11:31:55 +00:00
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2019-04-14 18:01:42 +00:00
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