Merge branch 'master' of github.com:r0ket/r0ket

firmware/l0dable/worksh.c

@@ -0,0 +1,132 @@
+/*
+ * geigerct.c
+ *
+ *
+ *  Created on: 11.08.2011
+ *      Author: Turbo J <turboj@web.de>
+ *
+ *  Implements simple Geiger Counter
+ *  Counts rising edges on P3_0 = BUSINT
+ *  so you can directly connect the Geiger board
+ *  from http://mightyohm.com/blog/products/geiger-counter/
+ *
+ */
+
+#include <sysinit.h>
+#include <string.h>
+
+#include "basic/basic.h"
+#include "basic/config.h"
+
+#include "lcd/render.h"
+#include "lcd/print.h"
+
+#include "usetable.h"
+
+// Liberated from ARM Cortex M3 CMSIS core_cm3.h
+// The processor definition headers for R0ket are incomplete :-/
+
+#define __I
+#define __IO volatile
+
+typedef struct {
+	__I uint32_t CPUID; /*!< Offset: 0x000 (R/ )  CPU ID Base Register                                  */
+	__IO uint32_t ICSR; /*!< Offset: 0x004 (R/W)  Interrupt Control State Register                      */
+	__IO uint32_t VTOR; /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+	__IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W)  Application Interrupt / Reset Control Register        */
+	__IO uint32_t SCR; /*!< Offset: 0x010 (R/W)  System Control Register                               */
+	__IO uint32_t CCR; /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+	__IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+	__IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+	__IO uint32_t CFSR; /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+	__IO uint32_t HFSR; /*!< Offset: 0x02C (R/W)  Hard Fault Status Register                            */
+	__IO uint32_t DFSR; /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+	__IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W)  Mem Manage Address Register                           */
+	__IO uint32_t BFAR; /*!< Offset: 0x038 (R/W)  Bus Fault Address Register                            */
+	__IO uint32_t AFSR; /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+	__I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+	__I uint32_t DFR; /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+	__I uint32_t ADR; /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+	__I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+	__I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ )  ISA Feature Register                                  */
+} SCB_Type;
+
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+#define SCB                 ((SCB_Type *)           SCB_BASE)         /*!< SCB configuration struct          */
+
+uint32_t VectorTableInRAM[73] __attribute__ ((aligned(1024))); // VTOR needs 1024 Byte alignment, see UM10375.PDF
+
+void (*orig_handler)(void);  // original EINT3 handler
+
+void TIMER32_0_IRQHandler(void);
+
+// Remember: ram() must be the first function, place all other code AFTER
+// because the Implementer seem not to know how to use section attributes
+
+static void mainloop();
+
+void ram(void) {
+	uint8_t button;
+	uint32_t LEDs;
+
+	// populate my Vector table
+	memcpy(VectorTableInRAM, 0, sizeof(VectorTableInRAM));
+	orig_handler = (void*) VectorTableInRAM[TIMER_32_0_IRQn + 16];
+	VectorTableInRAM[TIMER_32_0_IRQn + 16] = (uint32_t) &TIMER32_0_IRQHandler;
+	// HACK: use RAM vector table to implement own IRQ handler
+	SCB->VTOR = (uint32_t) &VectorTableInRAM[0];
+	// TODO add DMB() here, as VTOR updates are NOT effective immediately
+	//
+	NVIC_EnableIRQ(TIMER_32_0_IRQn);
+    
+    /* Enable the clock for CT32B0 */
+    SCB_SYSAHBCLKCTRL |= (SCB_SYSAHBCLKCTRL_CT32B0);
+    TMR_TMR32B0MR0  = (72E6/5E3)/2;
+    TMR_TMR32B0MCR = (TMR_TMR32B0MCR_MR0_INT_ENABLED | TMR_TMR32B0MCR_MR0_RESET_ENABLED);
+    TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_ENABLED;
+
+	mainloop();
+
+	NVIC_DisableIRQ(TIMER_32_0_IRQn);
+    TMR_TMR32B0TCR = TMR_TMR32B0TCR_COUNTERENABLE_DISABLED;
+	// restore VTOR
+	SCB->VTOR = 0;
+	//TODO DMB(); Cortex Manual suggests DMB after setting VTOR
+	// not really needed in this case
+}
+
+void TIMER32_0_IRQHandler(void)
+{
+    TMR_TMR32B0IR = TMR_TMR32B0IR_MR0;
+    static int time=0;
+    if (time==0){time=1;} else {time=0;}
+    gpioSetValue (RB_LED2, time);
+    gpioSetValue (RB_SPI_SS3, time);
+}
+
+static void mainloop(void) {
+    int dx=0;
+	int dy=0;
+    static uint32_t ctr=0;
+	ctr++;
+
+	setExtFont(GLOBAL(nickfont));
+	dx=DoString(0,0,GLOBAL(nickname));
+    dx=(RESX-dx)/2;
+    if(dx<0)
+        dx=0;
+    dy=(RESY-getFontHeight())/2;
+
+	lcdClear();
+    lcdSetPixel(1,1,1);
+	DoString(dx,dy,GLOBAL(nickname));
+	lcdRefresh();
+
+    while(getInputRaw()==BTN_NONE){
+        delayms_queue_plus(10,0);
+    };
+    return;
+}
+
+