From a03f202e7c0cd88bdd0560976820fb8d21529ee7 Mon Sep 17 00:00:00 2001
From: Stefan `Sec` Zehl <sec@42.org>
Date: Tue, 5 Jul 2011 02:33:36 +0200
Subject: [PATCH] First attempt at nrf support code

---
 firmware/basic/basic.h    |   5 ++
 firmware/funk/Makefile    |  36 +++++++++++++
 firmware/funk/nrf24l01p.c | 103 ++++++++++++++++++++++++++++++++++++++
 firmware/funk/nrf24l01p.h |  96 +++++++++++++++++++++++++++++++++++
 4 files changed, 240 insertions(+)
 create mode 100644 firmware/funk/Makefile
 create mode 100644 firmware/funk/nrf24l01p.c
 create mode 100644 firmware/funk/nrf24l01p.h

diff --git a/firmware/basic/basic.h b/firmware/basic/basic.h
index d343862..4bd93ea 100644
--- a/firmware/basic/basic.h
+++ b/firmware/basic/basic.h
@@ -105,6 +105,11 @@
 #define RB_HB5			1,2
 #define RB_HB5_IO		IOCON_PIO1_2
 
+// Funk
+#define RB_NRF_CE		1,5
+#define RB_NRF_CE_IO		IOCON_PIO1_5
+#define RB_SPI_NRF_CS		1,10
+#define RB_SPI_NRF_CS_IO	IOCON_PIO1_10
 
 // Misc
 #define RB_BUSINT		3,0
diff --git a/firmware/funk/Makefile b/firmware/funk/Makefile
new file mode 100644
index 0000000..4fdde2b
--- /dev/null
+++ b/firmware/funk/Makefile
@@ -0,0 +1,36 @@
+##########################################################################
+# User configuration and firmware specific object files	
+##########################################################################
+
+OBJS =
+
+OBJS += nrf24l01p.o
+
+LIBNAME=funk
+
+##########################################################################
+# GNU GCC compiler flags
+##########################################################################
+ROOT_PATH?= ..
+INCLUDE_PATHS = -I$(ROOT_PATH) -I../core -I.
+
+include $(ROOT_PATH)/Makefile.inc
+
+LIBFILE=lib$(LIBNAME).a
+##########################################################################
+# Compiler settings, parameters and flags
+##########################################################################
+
+all: $(LIBFILE)
+
+$(LIBFILE): $(OBJS)
+	$(AR) rcs $@ $(OBJS)
+	
+%.o : %.c
+	$(CC) $(CFLAGS) -o $@ $<
+
+clean:
+	rm -f $(OBJS) $(LIBFILE)
+
+nrf24l01p.o: nrf24l01p.h
+
diff --git a/firmware/funk/nrf24l01p.c b/firmware/funk/nrf24l01p.c
new file mode 100644
index 0000000..45c37e1
--- /dev/null
+++ b/firmware/funk/nrf24l01p.c
@@ -0,0 +1,103 @@
+#include <basic/basic.h>
+#include <nrf24l01p.h>
+#include "core/ssp/ssp.h"
+
+#define CHANNEL_BEACON 81
+#define DEFAULT_SPEED R_RF_SETUP_DR_2M
+#define MAC_BEACON "BEACO"
+
+/*-----------------------------------------------------------------------*/
+/* Transmit a byte via SPI  (Platform dependent)                         */
+/*-----------------------------------------------------------------------*/
+void xmit_spi(uint8_t dat) {
+    sspSend(0, (uint8_t*) &dat, 1);
+}
+
+/*-----------------------------------------------------------------------*/
+/* Receive a byte from MMC via SPI  (Platform dependent)                 */
+/*-----------------------------------------------------------------------*/
+uint8_t rcvr_spi (void) {
+    uint8_t data = 0;
+
+    sspReceive(0, &data, 1);
+
+    return data;
+}
+
+#define rcvr_spi_m(dst) \
+        do { \
+                    sspReceive(0, (uint8_t*)(dst), 1); \
+                } while(0)
+
+#define CS_LOW()    gpioSetValue(RB_SPI_NRF_CS, 0)
+#define CS_HIGH()   gpioSetValue(RB_SPI_NRF_CS, 1)
+
+void nrf_cmd(uint8_t cmd){
+    xmit_spi(cmd);
+};
+
+uint8_t nrf_cmd_status(uint8_t cmd){
+    xmit_spi(cmd);
+    return rcvr_spi();
+};
+
+void nrf_write_reg(uint8_t reg, uint8_t val){
+    xmit_spi(C_W_REGISTER | reg);
+    xmit_spi(val);
+};
+
+uint8_t nrf_read_reg(uint8_t reg, uint8_t val){
+    xmit_spi(C_R_REGISTER | reg);
+    // do i need to read the status byte here?
+    xmit_spi(val);
+    return rcvr_spi();
+};
+
+void nrf_write_reg_long(uint8_t reg, int len, char* data){
+    xmit_spi(C_W_REGISTER | reg);
+    for(int i=0;i<len;i++){
+        xmit_spi(data[i]);
+    };
+};
+
+void nrf_init() {
+    // Enable SPI correctly
+    sspInit(0, sspClockPolarity_Low, sspClockPhase_RisingEdge);
+
+    // Enable CS & CE pins
+    gpioSetDir(RB_SPI_NRF_CS, gpioDirection_Output);
+    gpioSetPullup(&RB_SPI_NRF_CS_IO, gpioPullupMode_Inactive);
+    gpioSetDir(RB_NRF_CE, gpioDirection_Output);
+    gpioSetPullup(&RB_NRF_CE_IO, gpioPullupMode_PullUp);
+
+    // Setup for nrf24l01+
+    // power up takes 1.5ms - 3.5ms (depending on crystal)
+    nrf_write_reg(R_CONFIG,
+            R_CONFIG_PRIM_RX| // Receive mode
+            R_CONFIG_PWR_UP|  // Power on
+            R_CONFIG_CRCO     // 2-byte CRC
+            );
+    
+    nrf_write_reg(R_EN_AA, 0); // Disable Enhanced ShockBurst;
+
+    nrf_write_reg(R_RF_CH, CHANNEL_BEACON &127); // Select channel
+
+    // enable receive pipes
+    nrf_write_reg(R_EN_RXADDR,R_EN_RXADDR_ERX_P0 
+//            |R_EN_RXADDR_ERX_P1
+            );
+
+    nrf_write_reg(R_RX_PW_P0,16);
+    nrf_write_reg_long(R_RX_ADDR_P0,5,"\x1\x2\x3\x2\1");
+
+//    nrf_write_reg(R_RX_PW_P1,16);
+//    nrf_write_reg_long(R_RX_ADDR_P1,5,"R0KET");
+
+    // OpenBeacon transmit address
+    nrf_write_reg_long(R_TX_ADDR,5,MAC_BEACON);
+
+    // Set speed / strength
+    nrf_write_reg(R_RF_SETUP,DEFAULT_SPEED|R_RF_SETUP_RF_PWR_3);
+
+    // XXX: or write R_CONFIG last?
+};
diff --git a/firmware/funk/nrf24l01p.h b/firmware/funk/nrf24l01p.h
new file mode 100644
index 0000000..454d28f
--- /dev/null
+++ b/firmware/funk/nrf24l01p.h
@@ -0,0 +1,96 @@
+#ifndef _NRF24L01P_H
+#define _NRF24L01P_H 1
+
+// SPI commands
+#define C_R_REGISTER		0x00
+#define C_W_REGISTER		0x20
+#define C_R_RX_PAYLOAD		0x61
+#define C_W_TX_PAYLOAD		0xA0
+#define C_FLUSH_TX		0xE1
+#define C_FLUSH_RX		0xE2
+#define C_REUSE_TX_PL		0xE3
+#define C_R_RX_PL_WID		0x60
+#define C_W_ACK_PAYLOAD		0xA8
+#define C_W_TX_PAYLOAD_NOCACK	0xB0
+#define C_NOP			0xFF
+
+// Registers
+#define R_CONFIG		0x00
+#define R_EN_AA			0x01
+#define R_EN_RXADDR		0x02
+#define R_SETUP_AW		0x03
+#define R_SETUP_RETR		0x04
+#define R_RF_CH			0x05
+#define R_RF_SETUP		0x06
+#define R_STATUS		0x07
+#define R_OBSERVE_TX		0x08
+#define R_RPD			0x09
+#define R_RX_ADDR_P0		0x0A
+ #define R_RX_ADDR_P0_LEN 5
+#define R_RX_ADDR_P1		0x0B
+ #define R_RX_ADDR_P1_LEN 5
+#define R_RX_ADDR_P2		0x0C
+ #define R_RX_ADDR_P2_LEN 1
+#define R_RX_ADDR_P3		0x0D
+ #define R_RX_ADDR_P3_LEN 1
+#define R_RX_ADDR_P4		0x0E
+ #define R_RX_ADDR_P4_LEN 1
+#define R_RX_ADDR_P5		0x0F
+ #define R_RX_ADDR_P5_LEN 1
+#define R_TX_ADDR		0x10
+ #define R_TX_ADDR_LEN 5
+#define R_RX_PW_P0		0x11
+#define R_RX_PW_P1		0x12
+#define R_RX_PW_P2		0x13
+#define R_RX_PW_P3		0x14
+#define R_RX_PW_P4		0x15
+#define R_RX_PW_P5		0x16
+#define R_FIFO_STATUS		0x17
+#define R_DYNPD			0x1c
+
+// Register Flags
+
+//CONFIG register definitions
+#define R_CONFIG_RESERVED        0x80
+#define R_CONFIG_MASK_RX_DR      0x40
+#define R_CONFIG_MASK_TX_DS      0x20
+#define R_CONFIG_MASK_MAX_RT     0x10
+#define R_CONFIG_EN_CRC          0x08
+#define R_CONFIG_CRCO            0x04
+#define R_CONFIG_PWR_UP          0x02
+#define R_CONFIG_PRIM_RX         0x01
+
+//EN_AA register definitions
+#define R_EN_AA_ENAA_P5          0x20
+#define R_EN_AA_ENAA_P4          0x10
+#define R_EN_AA_ENAA_P3          0x08
+#define R_EN_AA_ENAA_P2          0x04
+#define R_EN_AA_ENAA_P1          0x02
+#define R_EN_AA_ENAA_P0          0x01
+#define R_EN_AA_ENAA_NONE        0x00
+
+//EN_RXADDR register definitions
+#define R_EN_RXADDR_ERX_P5       0x20
+#define R_EN_RXADDR_ERX_P4       0x10
+#define R_EN_RXADDR_ERX_P3       0x08
+#define R_EN_RXADDR_ERX_P2       0x04
+#define R_EN_RXADDR_ERX_P1       0x02
+#define R_EN_RXADDR_ERX_P0       0x01
+#define R_EN_RXADDR_ERX_NONE     0x00
+
+//RF_SETUP register definitions
+#define R_RF_CONT_WAVE           0x80
+#define R_RF_SETUP_RF_DR_LOW     0x20
+#define R_RF_SETUP_PLL_LOCK      0x10
+#define R_RF_SETUP_RF_DR_HIGH    0x08
+#define R_RF_SETUP_RF_PWR_0      0x00
+#define R_RF_SETUP_RF_PWR_1      0x02
+#define R_RF_SETUP_RF_PWR_2      0x04
+#define R_RF_SETUP_RF_PWR_3      0x06
+
+#define R_RF_SETUP_DR_1M         0x00
+#define R_RF_SETUP_DR_2M         0x08
+#define R_RF_SETUP_DR_250K       0x20
+
+
+#endif /* _NRF24L01P_H */