2011-05-13 13:14:21 +00:00
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/*****************************************************************************
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* i2c.h: Header file for NXP LPC11xx Family Microprocessors
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*
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* Copyright(C) 2006, NXP Semiconductor
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* Parts of this code are (C) 2010, MyVoice CAD/CAM Services
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* All rights reserved.
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*
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* History
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* 2006.07.19 ver 1.00 Preliminary version, first Release
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* 2010.07.19 ver 1.10 Rob Jansen - MyVoice CAD/CAM Services
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* Updated to reflect new code
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*
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******************************************************************************/
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#ifndef __I2C_H
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#define __I2C_H
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#include "projectconfig.h"
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/*
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* These are states returned by the I2CEngine:
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*
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* IDLE - is never returned but only used internally
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* PENDING - is never returned but only used internally in the I2C functions
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* ACK - The transaction finished and the slave returned ACK (on all bytes)
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* NACK - The transaction is aborted since the slave returned a NACK
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* SLA_NACK - The transaction is aborted since the slave returned a NACK on the SLA
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* this can be intentional (e.g. an 24LC08 EEPROM states it is busy)
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* or the slave is not available/accessible at all.
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* ARB_LOSS - Arbitration loss during any part of the transaction.
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* This could only happen in a multi master system or could also
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* identify a hardware problem in the system.
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*/
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#define I2CSTATE_IDLE 0x000
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#define I2CSTATE_PENDING 0x001
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#define I2CSTATE_ACK 0x101
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#define I2CSTATE_NACK 0x102
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#define I2CSTATE_SLA_NACK 0x103
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#define I2CSTATE_ARB_LOSS 0x104
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2011-07-21 21:03:11 +00:00
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#define FAST_MODE_PLUS 1
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2011-05-13 13:14:21 +00:00
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#define I2C_BUFSIZE 6
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#define MAX_TIMEOUT 0x00FFFFFF
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#define I2CMASTER 0x01
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#define I2CSLAVE 0x02
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#define SLAVE_ADDR 0xA0
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#define READ_WRITE 0x01
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#define RD_BIT 0x01
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#define I2CONSET_I2EN 0x00000040 /* I2C Control Set Register */
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#define I2CONSET_AA 0x00000004
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#define I2CONSET_SI 0x00000008
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#define I2CONSET_STO 0x00000010
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#define I2CONSET_STA 0x00000020
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#define I2CONCLR_AAC 0x00000004 /* I2C Control clear Register */
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#define I2CONCLR_SIC 0x00000008
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#define I2CONCLR_STAC 0x00000020
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#define I2CONCLR_I2ENC 0x00000040
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#define I2DAT_I2C 0x00000000 /* I2C Data Reg */
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#define I2ADR_I2C 0x00000000 /* I2C Slave Address Reg */
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#define I2SCLH_SCLH 120 /* I2C SCL Duty Cycle High Reg */
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#define I2SCLL_SCLL 120 /* I2C SCL Duty Cycle Low Reg */
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#define I2SCLH_HS_SCLH 0x00000020 /* Fast Plus I2C SCL Duty Cycle High Reg */
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#define I2SCLL_HS_SCLL 0x00000020 /* Fast Plus I2C SCL Duty Cycle Low Reg */
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extern volatile uint8_t I2CMasterBuffer[I2C_BUFSIZE];
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extern volatile uint8_t I2CSlaveBuffer[I2C_BUFSIZE];
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2011-08-12 21:46:19 +00:00
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extern volatile uint32_t I2CReadLength;
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extern volatile uint32_t I2CWriteLength;
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2011-05-13 13:14:21 +00:00
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extern void I2C_IRQHandler( void );
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2011-08-12 21:46:19 +00:00
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uint32_t i2cInit( uint32_t I2cMode );
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uint32_t i2cEngine( void );
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2011-05-13 13:14:21 +00:00
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#endif /* end __I2C_H */
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/****************************************************************************
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** End Of File
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*****************************************************************************/
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