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bikegenerator/display/software/powerboard/main.lss

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main.elf: file format elf32-avr
Sections:
Idx Name Size VMA LMA File off Algn
0 .text 000001a0 00000000 00000000 00000074 2**1
CONTENTS, ALLOC, LOAD, READONLY, CODE
1 .bss 00000002 00800060 00800060 00000214 2**0
ALLOC
2 .stab 000006cc 00000000 00000000 00000214 2**2
CONTENTS, READONLY, DEBUGGING
3 .stabstr 00000054 00000000 00000000 000008e0 2**0
CONTENTS, READONLY, DEBUGGING
4 .debug_aranges 00000060 00000000 00000000 00000934 2**0
CONTENTS, READONLY, DEBUGGING
5 .debug_pubnames 000000d4 00000000 00000000 00000994 2**0
CONTENTS, READONLY, DEBUGGING
6 .debug_info 0000040e 00000000 00000000 00000a68 2**0
CONTENTS, READONLY, DEBUGGING
7 .debug_abbrev 000002a5 00000000 00000000 00000e76 2**0
CONTENTS, READONLY, DEBUGGING
8 .debug_line 00000384 00000000 00000000 0000111b 2**0
CONTENTS, READONLY, DEBUGGING
9 .debug_frame 000000d0 00000000 00000000 000014a0 2**2
CONTENTS, READONLY, DEBUGGING
10 .debug_str 000001cd 00000000 00000000 00001570 2**0
CONTENTS, READONLY, DEBUGGING
11 .debug_loc 0000017b 00000000 00000000 0000173d 2**0
CONTENTS, READONLY, DEBUGGING
12 .debug_pubtypes 000000ac 00000000 00000000 000018b8 2**0
CONTENTS, READONLY, DEBUGGING
Disassembly of section .text:
00000000 <__vectors>:
0: 12 c0 rjmp .+36 ; 0x26 <__ctors_end>
2: 21 c0 rjmp .+66 ; 0x46 <__bad_interrupt>
4: 20 c0 rjmp .+64 ; 0x46 <__bad_interrupt>
6: 1f c0 rjmp .+62 ; 0x46 <__bad_interrupt>
8: 1e c0 rjmp .+60 ; 0x46 <__bad_interrupt>
a: 1d c0 rjmp .+58 ; 0x46 <__bad_interrupt>
c: 3e c0 rjmp .+124 ; 0x8a <__vector_6>
e: 1b c0 rjmp .+54 ; 0x46 <__bad_interrupt>
10: 1a c0 rjmp .+52 ; 0x46 <__bad_interrupt>
12: 19 c0 rjmp .+50 ; 0x46 <__bad_interrupt>
14: 18 c0 rjmp .+48 ; 0x46 <__bad_interrupt>
16: 17 c0 rjmp .+46 ; 0x46 <__bad_interrupt>
18: 16 c0 rjmp .+44 ; 0x46 <__bad_interrupt>
1a: 15 c0 rjmp .+42 ; 0x46 <__bad_interrupt>
1c: 14 c0 rjmp .+40 ; 0x46 <__bad_interrupt>
1e: 13 c0 rjmp .+38 ; 0x46 <__bad_interrupt>
20: 12 c0 rjmp .+36 ; 0x46 <__bad_interrupt>
22: 11 c0 rjmp .+34 ; 0x46 <__bad_interrupt>
24: 10 c0 rjmp .+32 ; 0x46 <__bad_interrupt>
00000026 <__ctors_end>:
26: 11 24 eor r1, r1
28: 1f be out 0x3f, r1 ; 63
2a: cf e5 ldi r28, 0x5F ; 95
2c: d4 e0 ldi r29, 0x04 ; 4
2e: de bf out 0x3e, r29 ; 62
30: cd bf out 0x3d, r28 ; 61
00000032 <__do_clear_bss>:
32: 10 e0 ldi r17, 0x00 ; 0
34: a0 e6 ldi r26, 0x60 ; 96
36: b0 e0 ldi r27, 0x00 ; 0
38: 01 c0 rjmp .+2 ; 0x3c <.do_clear_bss_start>
0000003a <.do_clear_bss_loop>:
3a: 1d 92 st X+, r1
0000003c <.do_clear_bss_start>:
3c: a2 36 cpi r26, 0x62 ; 98
3e: b1 07 cpc r27, r17
40: e1 f7 brne .-8 ; 0x3a <.do_clear_bss_loop>
42: 1f d0 rcall .+62 ; 0x82 <main>
44: ab c0 rjmp .+342 ; 0x19c <_exit>
00000046 <__bad_interrupt>:
46: dc cf rjmp .-72 ; 0x0 <__vectors>
00000048 <timer_init>:
volatile uint16_t syscounter = 0;
void timer_init(void) {
// clock is 8MHz
TCCR1B |= _BV(WGM12) | _BV(CS11) | _BV(CS10) ; // CTC Mode for Timer 1 (16Bit) with prescale of 64
48: 8e b5 in r24, 0x2e ; 46
4a: 8b 60 ori r24, 0x0B ; 11
4c: 8e bd out 0x2e, r24 ; 46
OCR1A = 1250; // 100Hz
4e: 82 ee ldi r24, 0xE2 ; 226
50: 94 e0 ldi r25, 0x04 ; 4
52: 9b bd out 0x2b, r25 ; 43
54: 8a bd out 0x2a, r24 ; 42
TIMSK = _BV(OCIE1A);
56: 80 e1 ldi r24, 0x10 ; 16
58: 89 bf out 0x39, r24 ; 57
sei(); // enable interrupts
5a: 78 94 sei
}
5c: 08 95 ret
0000005e <ports_init>:
void ports_init(void) {
DDR_SW |= _BV(LOADSW) | _BV(GENSW) | _BV(DUMPSW);
5e: 87 b3 in r24, 0x17 ; 23
60: 87 60 ori r24, 0x07 ; 7
62: 87 bb out 0x17, r24 ; 23
PORT_SW &= ~(_BV(LOADSW) | _BV(GENSW) | _BV(DUMPSW));
64: 88 b3 in r24, 0x18 ; 24
66: 88 7f andi r24, 0xF8 ; 248
68: 88 bb out 0x18, r24 ; 24
}
6a: 08 95 ret
0000006c <get_voltage>:
// voltage has a divider (12V - 56k - ADC - 27k - GND)
// so
uint8_t voltage = 0;
return voltage;
}
6c: 80 e0 ldi r24, 0x00 ; 0
6e: 08 95 ret
00000070 <get_power>:
uint8_t get_power(power_source source) {
uint16_t voltage = get_voltage();
uint16_t amperes;
if(source == generated) {
70: 88 23 and r24, r24
72: 11 f4 brne .+4 ; 0x78 <get_power+0x8>
amperes = adc_read_avg(AD_I_GEN, 4);
74: 81 e0 ldi r24, 0x01 ; 1
76: 01 c0 rjmp .+2 ; 0x7a <get_power+0xa>
} else {
amperes = adc_read_avg(AD_I_LOAD, 4);
78: 80 e0 ldi r24, 0x00 ; 0
7a: 64 e0 ldi r22, 0x04 ; 4
7c: 34 d0 rcall .+104 ; 0xe6 <adc_read_avg>
}
return 0;
}
7e: 80 e0 ldi r24, 0x00 ; 0
80: 08 95 ret
00000082 <main>:
int main(void) {
ports_init();
82: ed df rcall .-38 ; 0x5e <ports_init>
adc_init();
84: 19 d0 rcall .+50 ; 0xb8 <adc_init>
timer_init();
86: e0 df rcall .-64 ; 0x48 <timer_init>
88: ff cf rjmp .-2 ; 0x88 <main+0x6>
0000008a <__vector_6>:
return(0);
}
// system timer
SIGNAL(TIMER1_COMPA_vect) {
8a: 1f 92 push r1
8c: 0f 92 push r0
8e: 0f b6 in r0, 0x3f ; 63
90: 0f 92 push r0
92: 11 24 eor r1, r1
94: 8f 93 push r24
96: 9f 93 push r25
syscounter++;
98: 80 91 60 00 lds r24, 0x0060
9c: 90 91 61 00 lds r25, 0x0061
a0: 01 96 adiw r24, 0x01 ; 1
a2: 90 93 61 00 sts 0x0061, r25
a6: 80 93 60 00 sts 0x0060, r24
}
aa: 9f 91 pop r25
ac: 8f 91 pop r24
ae: 0f 90 pop r0
b0: 0f be out 0x3f, r0 ; 63
b2: 0f 90 pop r0
b4: 1f 90 pop r1
b6: 18 95 reti
000000b8 <adc_init>:
void adc_init(void) {
uint16_t dummyResult;
// AVCC with external capacitor at AREF pin
ADMUX = _BV(REFS0);
b8: 80 e4 ldi r24, 0x40 ; 64
ba: 87 b9 out 0x07, r24 ; 7
// set frequency prescaler to 8
ADCSRA = _BV(ADPS1) | _BV(ADPS0);
bc: 83 e0 ldi r24, 0x03 ; 3
be: 86 b9 out 0x06, r24 ; 6
// enable ADC
ADCSRA |= _BV(ADEN);
c0: 37 9a sbi 0x06, 7 ; 6
// make a dummy read out
ADCSRA |= _BV(ADSC);
c2: 36 9a sbi 0x06, 6 ; 6
while (ADCSRA & _BV(ADSC) ) {
c4: 36 99 sbic 0x06, 6 ; 6
c6: fe cf rjmp .-4 ; 0xc4 <adc_init+0xc>
}
// we have to read, otherwise the next result is not available
dummyResult = ADCW;
c8: 84 b1 in r24, 0x04 ; 4
ca: 95 b1 in r25, 0x05 ; 5
}
cc: 08 95 ret
000000ce <adc_read_single>:
uint16_t adc_read_single(uint8_t channel) {
ADMUX = (ADMUX & ~(0x1F)) | (channel & 0x1F);
ce: 97 b1 in r25, 0x07 ; 7
d0: 8f 71 andi r24, 0x1F ; 31
d2: 90 7e andi r25, 0xE0 ; 224
d4: 89 2b or r24, r25
d6: 87 b9 out 0x07, r24 ; 7
ADCSRA |= _BV(ADSC);
d8: 36 9a sbi 0x06, 6 ; 6
while (ADCSRA & (1<<ADSC) ) {
da: 36 99 sbic 0x06, 6 ; 6
dc: fe cf rjmp .-4 ; 0xda <adc_read_single+0xc>
}
return ADCW;
de: 24 b1 in r18, 0x04 ; 4
e0: 35 b1 in r19, 0x05 ; 5
}
e2: c9 01 movw r24, r18
e4: 08 95 ret
000000e6 <adc_read_avg>:
uint16_t adc_read_avg(uint8_t channel, uint8_t nsamples) {
e6: bf 92 push r11
e8: cf 92 push r12
ea: df 92 push r13
ec: ef 92 push r14
ee: ff 92 push r15
f0: 0f 93 push r16
f2: 1f 93 push r17
f4: d8 2e mov r13, r24
f6: b6 2e mov r11, r22
uint32_t sum = 0;
for (uint8_t i=0; i<nsamples;++i ) {
f8: cc 24 eor r12, r12
}
return ADCW;
}
uint16_t adc_read_avg(uint8_t channel, uint8_t nsamples) {
uint32_t sum = 0;
fa: ee 24 eor r14, r14
fc: ff 24 eor r15, r15
fe: 87 01 movw r16, r14
for (uint8_t i=0; i<nsamples;++i ) {
100: 0a c0 rjmp .+20 ; 0x116 <adc_read_avg+0x30>
sum += adc_read_single(channel);
102: 8d 2d mov r24, r13
104: e4 df rcall .-56 ; 0xce <adc_read_single>
106: ac 01 movw r20, r24
108: 60 e0 ldi r22, 0x00 ; 0
10a: 70 e0 ldi r23, 0x00 ; 0
10c: e4 0e add r14, r20
10e: f5 1e adc r15, r21
110: 06 1f adc r16, r22
112: 17 1f adc r17, r23
}
uint16_t adc_read_avg(uint8_t channel, uint8_t nsamples) {
uint32_t sum = 0;
for (uint8_t i=0; i<nsamples;++i ) {
114: c3 94 inc r12
116: cb 14 cp r12, r11
118: a0 f3 brcs .-24 ; 0x102 <adc_read_avg+0x1c>
sum += adc_read_single(channel);
}
return (uint16_t)(sum / nsamples);
11a: 2b 2d mov r18, r11
11c: 30 e0 ldi r19, 0x00 ; 0
11e: 40 e0 ldi r20, 0x00 ; 0
120: 50 e0 ldi r21, 0x00 ; 0
122: c8 01 movw r24, r16
124: b7 01 movw r22, r14
126: 18 d0 rcall .+48 ; 0x158 <__udivmodsi4>
}
128: c9 01 movw r24, r18
12a: 1f 91 pop r17
12c: 0f 91 pop r16
12e: ff 90 pop r15
130: ef 90 pop r14
132: df 90 pop r13
134: cf 90 pop r12
136: bf 90 pop r11
138: 08 95 ret
0000013a <wait>:
#include <util/delay.h>
void wait(uint8_t count) {
uint8_t i;
if(count == 0) count = 100;
13a: 88 23 and r24, r24
13c: 09 f4 brne .+2 ; 0x140 <wait+0x6>
13e: 84 e6 ldi r24, 0x64 ; 100
for(i=0;i<count;i++) {
140: 90 e0 ldi r25, 0x00 ; 0
142: 07 c0 rjmp .+14 ; 0x152 <wait+0x18>
#else
//round up by default
__ticks_dc = (uint32_t)(ceil(fabs(__tmp)));
#endif
__builtin_avr_delay_cycles(__ticks_dc);
144: e3 ec ldi r30, 0xC3 ; 195
146: f9 e0 ldi r31, 0x09 ; 9
148: 31 97 sbiw r30, 0x01 ; 1
14a: f1 f7 brne .-4 ; 0x148 <wait+0xe>
14c: 00 c0 rjmp .+0 ; 0x14e <wait+0x14>
14e: 00 00 nop
150: 9f 5f subi r25, 0xFF ; 255
152: 98 17 cp r25, r24
154: b8 f3 brcs .-18 ; 0x144 <wait+0xa>
_delay_ms(10);
}
}
156: 08 95 ret
00000158 <__udivmodsi4>:
158: a1 e2 ldi r26, 0x21 ; 33
15a: 1a 2e mov r1, r26
15c: aa 1b sub r26, r26
15e: bb 1b sub r27, r27
160: fd 01 movw r30, r26
162: 0d c0 rjmp .+26 ; 0x17e <__udivmodsi4_ep>
00000164 <__udivmodsi4_loop>:
164: aa 1f adc r26, r26
166: bb 1f adc r27, r27
168: ee 1f adc r30, r30
16a: ff 1f adc r31, r31
16c: a2 17 cp r26, r18
16e: b3 07 cpc r27, r19
170: e4 07 cpc r30, r20
172: f5 07 cpc r31, r21
174: 20 f0 brcs .+8 ; 0x17e <__udivmodsi4_ep>
176: a2 1b sub r26, r18
178: b3 0b sbc r27, r19
17a: e4 0b sbc r30, r20
17c: f5 0b sbc r31, r21
0000017e <__udivmodsi4_ep>:
17e: 66 1f adc r22, r22
180: 77 1f adc r23, r23
182: 88 1f adc r24, r24
184: 99 1f adc r25, r25
186: 1a 94 dec r1
188: 69 f7 brne .-38 ; 0x164 <__udivmodsi4_loop>
18a: 60 95 com r22
18c: 70 95 com r23
18e: 80 95 com r24
190: 90 95 com r25
192: 9b 01 movw r18, r22
194: ac 01 movw r20, r24
196: bd 01 movw r22, r26
198: cf 01 movw r24, r30
19a: 08 95 ret
0000019c <_exit>:
19c: f8 94 cli
0000019e <__stop_program>:
19e: ff cf rjmp .-2 ; 0x19e <__stop_program>
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